DS1371 Datasheet, PDF (3/14 Pages) Maxim Integrated Products – 2-Wire, 32-Bit Binary Counter Watchdog Clock

DS1371
AC ELECTRICAL CHARACTERISTICS
(V_CC = 1.7V to 5.5V, T_A = -40°C to +85°C, unless otherwise noted.) (Note 8)
PARAMETER
SYMBOL CONDITIONS
SCL Clock Frequency (Note 9)
f_SCL
Fast mode
Standard mode
Bus Free Time Between STOP and
START Conditions
Hold Time (repeated) START Condition
(Note 10)
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 11, 12)
Data Setup Time (Note 13)
Start Setup Time
t_BUF
t_HD:STA
t_LOW
t_HIGH
t_HD:DAT
t_SU:DAT
t_SU:STA
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Rise Time of Both SDA and SCL
Signals (Note 9)
Fast mode
t_R
Standard mode
Fall Time of Both SDA and SCL Signals
(Note 9)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
(Note 7)
Pulse Width of Spikes that Must be
Suppressed by the Input Filter (Note 14)
Watchdog Strobe (WDS) Pulse Width
t_F
t_SU:STO
C_B
T_SP
t_WDS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
MIN
100
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
20 +
0.1C_B
0.6
4.7
100
Oscillator Stop Flag (OSF) Delay
(Note 8)
t_OSF
100
TYP
MAX
400
100
UNITS
kHz
ms
ms
ms
ms
0.9
0.9
ms
ns
ms
300
ns
1000
300
ns
300
ms
400
pF
30
ns
ns
ms
Note 1: All voltages are referenced to ground.
Note 2: SCL and WDS only.
Note 3: SDA and SQW/INT.
Note 4: Limits at -40°C are guaranteed by design and not production tested.
Note 5: ICCA—SCL clocking at max frequency = 400kHz. WDS inactive.
Note 6: Specified with WDS input and 2-wire bus inactive, SCL = SDA = VCC.
Note 7: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 8: The parameter tOSF is the period of time the oscillator must be stopped in order for the OSF flag to be set over the voltage range of 1.3V
≤ VCC ≤ VCCMAX.
Note 9: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of
the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Note 12: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13: CB—total capacitance of one bus line in pF.
Note 14: This parameter is not production tested.
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