DS1371 Datasheet, PDF (11/14 Pages) Maxim Integrated Products – 2-Wire, 32-Bit Binary Counter Watchdog Clock

DS1371
Status Register (08h)
Bit #
7
6
5
4
3
2
1
0
Name
OSF
0
0
0
0
0
0
AF
Default
1
0
0
0
0
0
0
—
Bit 7/Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or
was stopped for some period and can be used to judge the validity of the timekeeping data. This bit is set
to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the
OSF bit to be set:
· The first time power is applied.
· The voltage present on V_CC is insufficient to support oscillation.
· The EOSC bit is turned off.
· External influences on the crystal (e.g., noise, leakage, etc.)
· This bit remains at logic 1 until written to logic 0.
Bit 0/Alarm Flag (AF). A logic 1 in the AF bit indicates that the WD/ALM counter reached 0. If INTCN
is set to a 1, and WD/ALM is set to 0 and AIE is set to 1, the SQW/INT pin goes low and stays low until
AF is cleared. AF is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to
write logic 1 leaves the value unchanged. If INTCN and WD/ALM are set to 1 and the AIE is set to 1, the
SQW/INT pin pulses low for 250ms when the WD/ALM counter reaches 0 and sets AF = 1. At the
completion of the 250ms pulse, the DS1371 clears the AF bit to a 0. If the 250ms pulse is active, writing
AF to a 0 does not truncate the pulse.
2-Wire Serial Interface
The DS1371 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1371 operates as a slave on the 2-wire bus.
Connections to the bus are made through the open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (Figure 5):
· Data transfer can be initiated only when the bus is not busy.
· During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data line from low to high, while the clock line is high,
defines a STOP condition.
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