DS1308 Datasheet, PDF (9/16 Pages) Dallas Semiconductor – 64 X 8 Serial Real Time Clock

DS1308
Low-Current I²C RTC with 56-Byte NV RAM
Freshness Seal Mode
When a battery is first attached to the device, the device
does not immediately provide battery-backup power to
the RTC or internal circuitry. After VCC exceeds VPF,
the devices leave the freshness seal mode and provide
battery-backup power whenever VCC subsequently falls
below VBAT. This mode allows attachment of the battery
during product manufacturing, but no battery capacity is
consumed until after the system has been activated for
the first time. As a result, minimum battery energy is used
during storage and shipping.
Oscillator Circuit
The DS1308 uses an external 6pF 32.768kHz crystal. The
oscillator circuit does not require any external resistors or
capacitors to operate. See Table 2 for the external crystal
parameters. The Functional Diagram shows a simplified
schematic of the oscillator circuit. The startup time is
usually less than 1 second when using a crystal with the
specified characteristics.
Whenever V_CC > V_PF, a 5Fs glitch filter at the output of
the crystal oscillator is enabled.
Clock Accuracy
The accuracy of the clock is dependent upon the
accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Crystal frequency drift caused by temperature shifts
creates additional error. External circuit noise coupled
into the oscillator circuit can result in the clock running
fast. Figure 3 shows a typical PCB layout for isolating
the crystal and oscillator from noise. Refer to Application
Note 58: Crystal Considerations with Maxim Real-Time
Clocks (RTCs) for detailed information.
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
Table 1. Power Control
SUPPLY CONDITION
V_CC < V_PF, V_CC < V_BAT
V_CC < V_PF, V_CC > V_BAT
V_CC > V_PF, V_CC < V_BAT
V_CC > V_PF, V_CC > V_BAT
READ/WRITE
ACCESS
No
No
Yes
Yes
POWERED
BY
V_BAT
V_CC
V_CC
V_CC
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND
QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE PACKAGE.
Figure 3. Typical PCB Layout for Crystal
Table 2. Crystal Specifications
PARAMETER
SYMBOL MIN TYP MAX UNITS
Nominal Frequency
Series Resistance
f_O
32.768
kHz
ESR
100
kI
Load Capacitance
C_L
6
pF
Note: The crystal, traces, and crystal input pins should be isolated from RF generat-
ing signals. Refer to Application Note 58: Crystal Considerations for Maxim Real-Time
Clocks (RTCs) for additional specifications.
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