DS1308 Datasheet, PDF (11/16 Pages) Dallas Semiconductor – 64 X 8 Serial Real Time Clock

DS1308
Low-Current I²C RTC with 56-Byte NV RAM
Control Register (07h)
The control register controls the operation of the SQW/CLKIN pin and provides oscillator status.
Bit #
Name
POR
BIT 7
OUT
1
BIT 6
ECLK
0
BIT 5
OSF
1
BIT 4
SQWE
1
BIT 3
LOS
1
BIT 2
BBCLK
1
BIT 1
RS1
1
BIT 0
RS0
1
Bit 7: Output Control (OUT). Controls the output level of the SQW/CLKIN pin when the square-wave output is disabled
and V_CC>V_PF. If SQWE = 0, the logic level on the SQW/CLKIN pin is 1 if OUT = 1; it is 0 if OUT = 0. See Table 4.
Bit 6: Enable Clock Input (ECLK). This bit controls the direction of the SQW/CLKIN pin (see Table 4). When ECLK = 1,
the SQW/CLKIN pin is an input, with the expected input rate defined by the states of RS1 and RS0. When ECLK = 0, the
SQW/CLKIN pin is an output, with the square-wave frequency defined by the states of RS1 and RS0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some
time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set
to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition.
The following are examples of conditions that may cause the OSF bit to be set:
The first time power is applied.
The voltage present on V_CC and V_BAT are insufficient to support oscillation.
The CH bit is set to 1, disabling the oscillator.
External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1
leaves the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either
V_CC or V_BAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits.
Bit 3: Loss of Signal (LOS). This status bit indicates the state of the CLKIN pin. The LOS bit is set to 1 when the RTC
counter is no longer conditioned by the external clock. This occurs when 1) ECLK = 0, or 2) when the CLKIN input signal
stops toggling, or 3) when the CLKIN frequency differs by more than Q0.8% from the selected input frequency. This bit
remains a 1 until written to 0. Attempting to write LOS = 1 leaves the value unchanged. Clearing the LOS flag when the
CLKIN frequency is invalid inhibits subsequent detections of the input frequency deviation.
Bit 2: Battery Backup Clock (BBCLK). When set to logic 1, this bit enables the SQW/CLKIN I/O while the part is pow-
ered by V_BAT. When set to logic 0, this bit disables the SQW/CLKIN I/O while the part is powered by V_BAT.
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the SQW/CLKIN output when the square-
wave has been enabled (SQWE = 1). Table 4 lists the square-wave frequencies that can be selected with the RS bits.
Table 4. SQW/CLKIN Pin Functions
OUT
ECLK
SQWE
RS1
RS0
X
0
1
0
0
X
0
1
0
1
X
0
1
1
0
X
0
1
1
1
0
0
0
X
X
1
0
0
X
X
X
1
X
0
0
X
1
X
0
1
X
1
X
1
0
X
1
X
1
1
X = Don’t care.
SQW/CLKIN
1Hz output
4.096kHz output
8.192kHz output
32.768kHz output
0
1
1Hz input
50Hz input
60Hz input
32.768kHz input
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