DS12CR885 Datasheet, PDF (9/22 Pages) Maxim Integrated Products – RTC with Constant-Voltage Trickle Charger

RTC with Constant-Voltage Trickle Charger
X1
X2
DS12R887/
DS12CR887
ONLY
V_CC
V_BACKUP
GND
DS12R887/
DS12CR887
ONLY
CS
R/W
DS
AS
MOT
RESET
AD0–AD7
RLCR
OSC
POWER
CONTROL
AND
TRICKLE
CHARGER
BUS
INTERFACE
Functional Diagram
DIVIDE
BY 8
DIVIDE
BY 64
16:1 MUX
DS12R885
DIVIDE
BY 64
SQUARE-
SQW
WAVE
GENERATOR
IRQ
IRQ
GENERATOR
CLOCK/CALENDAR
UPDATE LOGIC
REGISTERS A, B, C, D
CLOCK/CALENDAR AND
ALARM REGISTERS
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
USER RAM
114 BYTES
Pin Description
SO
1
2
3
4–11
PIN
EDIP
1
—
—
4–11
BGA
C5
—
—
F4, D4,
F3, D3,
F2, D2,
F1, D1
NAME
MOT
X1
X2
AD0–
AD7
FUNCTION
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to V_CC, Motorola bus timing is selected. When connected to GND or left
disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor.
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a 12.5pF specified load capacitance (C_L). Pin
X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz
oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is
connected to pin X1.
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first
portion of the bus cycle and latched into the DS12R885 by the falling edge of AS. Write
data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel
timing). In a read cycle, the DS12R885 outputs data during the latter portion of DS (DS and
R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is
terminated and the bus returns to a high-impedance state as DS transitions low in the case
of Motorola timing or as DS transitions high in the case of Intel timing.
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