DS12CR885 Datasheet, PDF (20/22 Pages) Maxim Integrated Products – RTC with Constant-Voltage Trickle Charger

RTC with Constant-Voltage Trickle Charger
Table 3. Periodic Interrupt Rate and
Square-Wave Output Frequency
SELECT BITS
REGISTER A
RS3 RS2 RS1 RS0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
t_PI PERIODIC
INTERRUPT
RATE
None
3.90625ms
7.8125ms
122.070µs
244.141µs
488.281µs
976.5625µs
1.953125ms
3.90625ms
7.8125ms
15.625ms
31.25ms
62.5ms
125ms
250ms
500ms
SQW OUTPUT
FREQUENCY
None
256Hz
128Hz
8.192kHz
4.096kHz
2.048kHz
1.024kHz
512Hz
256Hz
128Hz
64Hz
32Hz
16Hz
8Hz
4Hz
2Hz
Update Cycle
The DS12R885 executes an update cycle once per
second regardless of the SET bit in Register B. When
the SET bit in Register B is set to 1, the user copy of the
double-buffered time, calendar, and alarm bytes is
frozen and does not update as the time increments.
However, the time countdown chain continues to
update the internal copy of the buffer. This feature
allows time to maintain accuracy independent of read-
ing or writing the time, calendar, and alarm buffers, and
also guarantees that time and calendar information is
consistent. The update cycle also compares each
alarm byte with the corresponding time byte and issues
an alarm if a match or if a don’t-care code is present in
all three positions.
There are three methods that can handle RTC access
that avoid any possibility of accessing inconsistent time
and calendar data. The first method uses the update-
ended interrupt. If enabled, an interrupt occurs after
every update cycle that indicates over 999ms is avail-
able to read valid time and date information. If this
interrupt is used, the IRQF bit in Register C should be
cleared before leaving the interrupt routine.
A second method uses the update-in-progress bit (UIP)
in Register A to determine if the update cycle is in
progress. The UIP bit pulses once per second. After
the UIP bit goes high, the update transfer occurs 244µs
later. If a low is read on the UIP bit, the user has at least
244µs before the time/calendar data is changed.
Therefore, the user should avoid interrupt service rou-
tines that would cause the time needed to read valid
time/calendar data to exceed 244µs.
The third method uses a periodic interrupt to determine
if an update cycle is in progress. The UIP bit in Register
A is set high between the setting of the PF bit in
Register C (Figure 3). Periodic interrupts that occur at a
rate greater than t_BUC allow valid time and date infor-
mation to be reached at each occurrence of the period-
ic interrupt. The reads should be complete within 1(t_PI/2
+ t_BUC) to ensure that data is not read during the
update cycle.
1 SECOND
UIP
t_BUC
UF
PF
t _PI
t_BUC = DELAY TIME BEFORE UPDATE
CYCLE = 244µs
Figure 3. UIP and Periodic Interrupt Timing
t_P1/2
t_P1/2
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