DS12CR885 Datasheet, PDF (10/22 Pages) Maxim Integrated Products – RTC with Constant-Voltage Trickle Charger

RTC with Constant-Voltage Trickle Charger
Pin Description (continued)
PIN
SO
EDIP
NAME
BGA
D5–D8,
12
12 E1–E8, GND Ground
F5–F8
FUNCTION
Chip-Select Input. The active-low chip-select signal must be asserted low for a bus cycle
in the DS12R885 to be accessed. CS must be kept in the active state during DS and AS
13
13
C1
CS
for Motorola timing and during DS and R/W for Intel timing. Bus cycles that take place
without asserting CS latch addresses, but no access occurs. When V_CC is below V_PF volts,
the DS12R885 inhibits access by internally disabling the CS input. This action protects the
RTC data and the RAM data during power outages.
Address Strobe Input. A positive-going address-strobe pulse serves to demultiplex the
bus. The falling edge of AS causes the address to be latched within the DS12R885. The
14
14
C3
AS
next rising edge that occurs on the AS bus clears the address regardless of whether CS is
asserted. An address strobe must immediately precede each write or read access. If a
write or read is performed with CS deasserted, another address strobe must be performed
prior to a read or write access with CS asserted.
Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is
connected to V_CC for Motorola timing, R/W is at a level that indicates whether the current
cycle is a read or write. A read cycle is indicated with a high level on R/W while DS is high.
15
15
C2
R/W A write cycle is indicated when R/W is low during DS. When the MOT pin is connected to
GND for Intel timing, the R/W signal is an active-low signal. In this mode, the R/W pin
operates in a similar fashion as the write-enable signal (WE) on generic RAMs. Data are
latched on the rising edge of the signal.
16, 22
2, 3, 16,
20–22
A3
N.C.
No Connection. This pin should remain unconnected. On the EDIP, these pins are missing
by design.
Data Strobe or Read Input. The DS pin has two modes of operation depending on the level of
the MOT pin. When the MOT pin is connected to V_CC, Motorola bus timing is selected. In this
mode, DS is a positive pulse during the latter portion of the bus cycle and is called data
17
17
A1
DS
strobe. During read cycles, DS signifies the time that the DS12R885 is to drive the
bidirectional bus. In write cycles, the trailing edge of DS causes the DS12R885 to latch the
written data. When the MOT pin is connected to GND, Intel bus timing is selected. DS
identifies the time period when the DS12R885 drives the bus with read data. In this mode, the
DS pin operates in a similar fashion as the output-enable (OE) signal on a generic RAM.
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