DS3105 Datasheet, PDF (86/110 Pages) Maxim Integrated Products – Line Card Timing IC

Preliminary. Subject to Change Without Notice.
DS3105
Register Name:
Register Description:
Register Address:
PBOFF
Phase Build-Out Offset Register
72h
Name
Default
Bit 7
--
0
Bit 6
--
0
Bit 5
0
Bit 4
0
Bit 3
Bit 2
PBOFF[5:0]
0
0
Bit 1
0
Bit 0
0
Bits 5 to 0: Phase Build-Out Offset Register (PBOFF[5:0]). An uncertainty of up to 5 ns is introduced each time
a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase
build-out events the mean error should be zero. The PBOFF field specifies a fixed offset for each phase build-out
event to skew the average error toward zero. This field is a 2’s complement signed integer. The offset in
nanoseconds is PBOFF[5:0] * 0.101. Values greater than 1.4 ns or less than –1.4 ns may cause internal math
errors and should not be used. See section 7.7.7.2.
Register Name:
Register Description:
Register Address:
PHLIM1
Phase Limit Register 1
73h
Name
Default
Bit 7
FLEN
1
Bit 6
NALOL
0
Bit 5
1
1
Bit 4
--
0
Bit 3
--
0
Bit 2
0
Bit 1
FINELIM[2:0]
1
Bit 0
0
Bit 7: Fine Phase Limit Enable (FLEN). This configuration bit enables the fine phase limit specified in the
FINELIM[2:0] field. The fine limit must be disabled for multi-UI jitter tolerance (see PHLIM2 fields). This field
controls both T0 and T4. See section 7.7.6.
0 = Disabled
1 = Enabled
Bit 6: No-Activity Loss of Lock (NALOL). The T0 and the T4 DPLLs can detect that an input clock has no activity
very quickly (within two clock cycles). When NALOL=0, loss-of-lock is not declared when clock cycles are missing,
and nearest edge locking (±180°) is used when the clock recovers. This gives tolerance to missing cycles. When
NALOL=1, loss-of-lock is indicated as soon as no activity is detected, and the device switches to phase/frequency
locking (±360°). This field controls both T0 and T4. See sections 7.5.3 and 7.7.6.
0 = No activity does not trigger loss-of-lock
1 = No activity does trigger loss-of-lock
Bit 5: Leave set to 1 (test control).
Bits 2 to 0: Fine Phase Limit (FINELIM[2:0]). This field specifies the fine phase limit window, outside of which
loss-of-lock is declared. The FLEN bit enables this feature. The phase of the input clock has to be inside the fine
limit window for two seconds before phase lock is declared. Loss-of-lock is declared immediately if the phase of the
input clock is outside the phase limit window. The default value of 010 is appropriate for most situations. This field
controls both T0 and T4. See section 7.7.6.
000 = Always indicates loss of phase lock—do not use
001 = Small phase limit window, ±45 to ±90°
010 = Normal phase limit window, ±90 to ±180° (default)
100, 101, 110, 111 = Proportionately larger phase limit window
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