DS3105 Datasheet, PDF (56/110 Pages) Maxim Integrated Products – Line Card Timing IC

Preliminary. Subject to Change Without Notice.
Register Name:
Register Description:
Register Address:
ISR3
Input Status Register 3
12h
Name
Default
Bit 7
--
0
Bit 6
--
0
Bit 5
ACT6
1
Bit 4
LOCK6
0
Bit 3
--
0
Bit 2
--
0
Bit 1
ACT5
1
This register has the same behavior as the and ISR2 registers, but for input clocks IC5 and IC6.
DS3105
Bit 0
LOCK5
0
Register Name:
Register Description:
Register Address:
ISR5
Input Status Register 5
14h
Name
Default
Bit 7
--
0
Bit 6
--
0
Bit 5
--
0
Bit 4
--
0
Bit 3
--
0
Bit 2
--
0
This register has the same behavior as the ISR2 register, but for input clock IC9.
Bit 1
ACT9
1
Bit 0
LOCK9
0
Register Name:
Register Description:
Register Address:
MSR4
Master Status Register 4
17h
Name
Default
Bit 7
--
0
Bit 6
HORDY
0
Bit 5
MRAA
0
Bit 4
--
0
Bit 3
--
0
Bit 2
--
0
Bit 1
--
0
Bit 0
--
0
Bit 6: Holdover Frequency Ready (HORDY). This latched status bit is set to 1 when the T0 DPLL has a holdover
value that has been averaged over the 1-second holdover averaging period. HORDY is cleared when written with a
1. When HORDY is set it can cause an interrupt request on the INTREQ pin if the HORDY interrupt enable bit is
set in the IER4 register. See section 7.7.1.6.
Bit 5: Multi-Register Access Aborted (MRAA). This latched status bit is set to 1 when a multi-byte access (read
or write) is interrupted by another access to the device. MRAA is cleared when written with a 1. MRAA cannot
cause an interrupt to occur. See section 8.3.
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