DS3105 Datasheet, PDF (21/110 Pages) Maxim Integrated Products – Line Card Timing IC

Preliminary. Subject to Change Without Notice.
DS3105
7.6.3 Forced Selection
The T0FORCE field in the MCR2 register and the T4FORCE field in the MCR4 register provide a way to force a
specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and
T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 3 to 6 and
9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally,
forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive
mode (MCR3:REVERT=1) the forced clock automatically becomes the selected reference (as specified in
PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected
reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive
and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when
no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority
input is listed as the third-highest priority (PTAB2:REF3).
When the T4 DPLL is used to measure the phase difference between the T0 DPLL selected reference and another
reference input by setting the T0CR1:T4MT0 bit, the T4FORCE field in the MCR4 register can be used to select the
other reference input.
7.6.4 Ultra-Fast Reference Switching
By default, disqualification of the selected reference and switchover to another reference occurs when the activity
monitor’s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of
milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also
available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects
approximately two missing clock cycles it declares the reference failed by forcing the leaky bucket accumulator to
its upper threshold (see section 7.5.2) and initiates reference switching. This is in addition to setting the SRFAIL
latched status bit in MSR2 and optionally generating an interrupt request, as described in section 7.5.3. When ultra-
fast switching occurs, the T0 DPLL transitions to the Pre-locked 2 state, which allows switching to occur faster by
bypassing the Loss-of-Lock state. The device should be in non-revertive mode when ultra-fast switching is enabled.
If the device is in revertive mode, ultra-fast switching could cause excessive reference switching when the highest
priority input is intermittent.
7.6.5 External Reference Switching Mode
In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by
setting the EXTSW bit to 1 in the MCR10 register. In this mode, if the SRCSW pin is high, the T0 DPLL is forced to
lock to input IC3 (if the priority of IC3 is non-zero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the
selected input has a valid reference signal. If the SRCSW pin is low the T0 DPLL is forced to lock to input IC4 (if
the priority of IC4 is non-zero in IPR2) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a
valid reference signal. During reset the default value of the EXTSW bit is latched from the SRCSW pin. If external
reference switching mode is enabled during reset, the default frequency tolerance (DLIMIT registers) is configured
to ±80 ppm rather than the normal default of ±9.2 ppm.
In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the
selected reference whether it is valid or not. Unlike forced reference selection (section 7.6.3) this mode controls the
PTAB1:SELREF field directly and is therefore not affected by the state of the MCR3:REVERT bit. During external
reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2 and REF3 fields in the PTAB
registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the
automatic selection logic. External reference switching mode only affects the T0 DPLL.
7.6.6 Output Clock Phase Continuity During Reference Switching
If phase build out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than
±30ppm then the device always complies with the GR-1244-CORE requirement that the rate of phase change must
be less than 81 ns per 1.326 ms during reference switching.
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