DS3105 Datasheet, PDF (24/110 Pages) Maxim Integrated Products – Line Card Timing IC

Preliminary. Subject to Change Without Notice.
Figure 7-2. T0 DPLL State Transition Diagram
DS3105
Reset
Free-Run
select ref
(001)
(selected reference invalid > 2s
OR out of lock >100s)
AND no valid input clock
all input clocks evaluated
at least one input valid
[selected reference invalid OR
out of lock >100s OR
(revertive mode AND valid higher-priority input)]
AND valid input clock available
Pre-locked
wait for <=100s
(110)
[selected reference invalid OR
(revertive mode AND valid higher-priority input)]
AND valid input clock available
phase-locked
to selected
reference > 2s
phase-locked to
selected reference > 2s
Locked
(100)
phase-lock regained
on selected reference
within 100s
loss-of-lock on
selected reference
selected reference invalid > 2s
AND
no valid input clock available
[selected reference invalid OR
(revertive mode AND valid higher-priority input)
(selected reference invalid > 2s
Pre-locked 2
wait for <=100s
OR out of lock >100s] AND
valid input clock available
OR out of lock >100s) AND
Loss-of-Lock _{no valid input clock available}
wait for <=100s
(101)
(111)
Holdover
select ref
(010)
[selected reference invalid OR
out of lock >100s OR
(revertive mode AND valid higher-priority input)]
AND valid input clock available
(selected reference invalid > 2s
OR out of lock >100s) AND
no valid input clock available
all input clocks evaluated
at least one input valid
Notes:
• An input clock is valid when it has no activity alarm and no phase lock alarm (see the VALSR registers and the ISR registers).
• All input clocks are continuously monitored for activity.
• Only the selected reference is monitored for loss of lock.
• Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds.
• To simply the diagram, the phase-lock time-out period is always shown as 100s, which is the default value of the PHLKTO register. Longer or
shorter time-out periods can be specified as needed by writing the appropriate value to the PHLKTO register.
• When selected reference is invalid and the DPLL is not in freerun or holdover, the DPLL is in a temporary holdover state.
7.7.1.3 Locked State
The T0 DPLL state machine can reach the locked state from the pre-locked, pre-locked 2 or loss-of-lock states
when the DPLL has locked to the selected reference for at least two seconds (see section 7.7.6). In the locked
state the output clocks track the phase and frequency of the selected reference.
If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the Locked state.
While in the locked state, if the selected reference is so impaired that an activity alarm is raised (corresponding
ACT bit set in the ISR register), then the selected reference is invalidated (ICn bit goes low in VALSR registers),
and the state machine immediately transitions to either the pre-locked 2 state (if another valid input clock is
available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).
If loss-of-lock (see section 7.7.6) is declared while in the locked state then the state machine transitions to the loss-
of-lock state.
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