DS3101 Datasheet, PDF (80/150 Pages) Dallas Semiconductor – Stratum 3/3E Timing Card IC

DS3101
Register Name:
Register Description:
Register Address:
MCR3
Master Configuration Register 3
34h
Name
Default
Bit 7
AEFSEN
1
Bit 6
LKATO
1
Bit 5
XOEDGE
0
Bit 4
MANHO
0
Bit 3
EFSEN
0
Bit 2
Bit 1
Bit 0
SONSDH MASTSLV REVERT
see below see below
0
Bit 7: Auto External Frame Sync Enable (AEFSEN). See Section 7.9.3.
0 = EFSEN bit (bit 3 below) enables and disables the external frame sync on the SYNC2K pin
1 = The external frame sync is enabled when EFSEN = 1 and the T0 DPLL is locked to the input clock
specified in the SOURCE field of FSCR3.
Bit 6: Phase Lock Alarm Timeout (LKATO). This bit controls how phase alarms on input clocks can be
terminated. Phase alarms are indicated by the LOCK bits in ISR registers
0 = Phase alarms on input clocks can only be cancelled by software
1 = Phase alarms are automatically cancelled after a timeout period of 128 seconds
Bit 5: Local Oscillator Edge (XOEDGE). This bit specifies the significant clock edge of the local oscillator clock
signal on the REFCLK input pin. The faster edge should be selected for best jitter performance. See Section 7.3.
0 = Rising edge
1 = Falling edge
Bit 4: Manual Holdover (MANHO). When this bit is set to 1 the T0 DPLL holdover frequency is set by the
HOFREQ field in the HOCR1, HOCR2 and HOCR3 registers. When MANHO = 1 it has priority over any other
holdover control fields. See Section 7.7.1.6.
0 = Standard holdover: holdover frequency is learned by the T0 DPLL from the selected reference
1 = Manual holdover: holdover frequency is taken from the HOFREQ field
Bit 3: External Frame Sync Enable (EFSEN). When this bit is set to 1 the T0 DPLL looks for a reference frame
sync pulse on the SYNC2K pin. See the AEFSEN bit description above for more information. See Section 7.9.3.
0 = Disable external frame sync; ignore SYNC2K pin
1 = Enable external frame sync on SYNC2K pin
Bit 2: SONET or SDH Frequencies (SONSDH). This bit specifies the clock rate for input clocks with FREQ=0001
in the ICR registers (20h to 2Dh). During reset the default value of this bit is latched from the SONSDH pin. See
Section 7.4.2.
0 = 2048kHz
1 = 1544 Hz
Bit 1: Master or Slave Configuration (MASTSLV). This read-only bit indicates the state of the MASTSLV pin.
This bit therefore does not have a fixed default value. To disable the master-slave pin feature and give software the
ability to configure devices as either master or slave, wire the MASTSLV pin high (master mode) on both devices.
See Section 7.9.
0 = Slave Mode. In this mode input clock IC11 is set to priority 1 (highest), the T0 DPLL is set to acquisition
bandwidth, revertive mode is enabled, and phase build-out is disabled.
1 = Master Mode. In this mode all setting are configured by configuration registers.
Bit 0: Revertive Mode (REVERT). This bit configures the T0 DPLL for revertive or non-revertive operation. (The
T4 DPLL is always revertive). In revertive mode, if an input clock with a higher priority than the selected reference
becomes valid, the higher-priority reference immediately becomes the selected reference. In nonrevertive mode,
the higher priority reference does not immediately become the selected reference but does become the highest-
priority reference in the priority table (REF1 field in the PTAB1 register). See Section 7.6.2.
When the device is in slave mode (MASTSLV pin = 0) values written to this field are latched, but the value read is
always 1 to indicate that the device is forced into revertive mode. See Section 7.9.1.
0 = Nonrevertive mode
1 = Revertive mode
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