DS3101 Datasheet, PDF (139/150 Pages) Dallas Semiconductor – Stratum 3/3E Timing Card IC

10.6 JTAG Interface Timing
Table 10-13. JTAG Interface Timing
(V_DD = 1.8V ±10%, V_DDIO = 3.3V ±5%, T_A = -40°C to +85°C.) (Note 1) (See Figure 10-7.)
PARAMETER
SYMBOL
MIN
TYP
MAX
JTCLK Clock Period
t1
1000
JTCLK Clock High/Low Time (Note 2)
t2/t3
50
500
JTCLK to JTDI, JTMS Setup Time
t4
50
JTCLK to JTDI, JTMS Hold Time
t5
50
JTCLK to JTDO Delay
t6
2
50
JTCLK to JTDO High-Z Delay (Note 3)
t7
2
50
JTRST Width Low Time
t8
100
Note 1:
Note 2:
Note 3:
The timing parameters in this table are guaranteed by design (GBD).
Clock can be stopped high or low.
Not tested during production test.
Figure 10-7. JTAG Timing Diagram
DS3101
UNITS
ns
ns
ns
ns
ns
ns
ns
t2
JTCLK
JTDI, JTMS, JTRST
JTDO
JTRST
t6
t7
t1
t3
t4
t5
t8
19-4596; Rev 4; 5/09
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