DS3101 Datasheet, PDF (1/150 Pages) Dallas Semiconductor – Stratum 3/3E Timing Card IC

19-4596; Rev 4; 5/09
DEMO KIT AVAILABLE
DS3101
Stratum 2/3E/3 Timing Card IC
www.maxim-ic.com
GENERAL DESCRIPTION
When paired with an external TCXO or OCXO, the
DS3101 is a highly integrated central timing and
synchronization solution for SONET/SDH network
elements. With 14 input clocks, the device directly
accepts both line timing from a large number of line
cards and external timing from external DS1/E1 BITS
transceivers. All input clocks are continuously monitored
for frequency accuracy and activity. Any two of the input
clocks can be selected as the references for the two
core DPLLs. The T0 DPLL complies with the Stratum 2,
3E, 3 4E and 4 requirements of GR-1244, GR-253,
G.812 Types I - IV, G.813 and G.8262. From the output
of the core DPLLs, a wide variety of output clock
frequencies and frame pulses can be produced
simultaneously on the 11 output clock pins. Two
DS3101 devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3101 registers and I/O pins are backward
compatible with Semtech’s ACS8520 and ACS8530
timing card ICs. The DS3101 is functionally equivalent
to a DS3100 without integrated BITS transceivers.
APPLICATIONS
SONET/SDH ADMs, MSPPs, and MSSPs
Digital Cross-Connects
DSLAMs
Service Provider Routers
FUNCTIONAL DIAGRAM
TIMING FROM
LINE CARDS AND
BITS/SSU RECEIVERS ₁₄
(VARIOUS RATES)
DS3101
SONET/SDH
SYNCHRONIZATION
11
IC
TIMING TO
LINE CARDS AND
BITS/SSU TRANSMITTERS
(VARIOUS RATES)
LOCAL TCXO
OR OCXO
CONTROL STATUS
FEATURES
 Synchronization Subsystem for Stratum 2, 3E,
3, 4E, and 4, SMC, SEC and EEC
- Meets Requirements of GR-1244 Stratum 2 - 4,
GR-253, G.812 Types I - IV, G.813 and G.8262
- Stratum 2, 3E or 3 Holdover Accuracy with
Suitable External Oscillator
- Programmable Bandwidth, 0.5mHz to 70Hz
- Hitless Reference Switching on Loss of Input
- Phase Build-Out and Transient Absorption
- Locks To and Generates 125MHz for Gigabit
Synchronous Ethernet per ITU-T G.8261
 14 Input Clocks
- 10 CMOS/TTL Inputs Accept 2kHz, 4kHz, and Any
Multiple of 8kHz Up to 125MHz
- Two LVDS/LVPECL/CMOS/TTL Inputs Accept
Nx8kHz Up to 125MHz Plus 155.52MHz
- Two 64kHz Composite Clock Receivers
- Continuous Input Clock Quality Monitoring
- Separate 2/4/8kHz Frame Sync Input
 11 Output Clocks
- Five CMOS/TTL Outputs Drive Any Internally
Produced Clock Up to 77.76MHz
- Two LVDS Outputs Each Drive Any Internally
Produced Clock Up to 311.04MHz
- One 64kHz Composite Clock Transmitter
- One 1.544MHz/2.048MHz Output Clock
- Two Sync Pulses: 8kHz and 2kHz
- Output Clock Rates Include 2kHz, 8kHz, NxDS1,
NxDS2, DS3, NxE1, E3, 6.48MHz, 19.44MHz,
38.88 MHz, 51.84MHz, 62.5MHz, 77.76MHz,
125MHz, 155.52MHz, 311.04MHz
 Internal Compensation for Master Clock
Oscillator Frequency Accuracy
 Processor Interface: 8-Bit Parallel or SPI Serial
 1.8V Operation with 3.3V I/O (5V Tolerant)
ORDERING INFORMATION
PART
DS3101GN
DS3101GN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 CSBGA (17mm)²
256 CSBGA (17mm)²
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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