DS3101 Datasheet, PDF (57/150 Pages) Dallas Semiconductor – Stratum 3/3E Timing Card IC

Figure 7-9. SPI Bus Transactions
Single-Byte Write
CS
SDI
SDO
R/W Register Address Burst Data Byte
0 (Write)
0 (single-byte)
Single-Byte Read
CS
SDI
SDO
R/W Register Address Burst
1 (Read)
0 (single-byte)
Data Byte
Burst Write
CS
SDI
SDO
R/W Register Address Burst Data Byte 1
0 (Write)
1 (burst)
Burst Read
CS
SDI
R/W Register Address Burst
1 (Read)
1 (burst)
Data Byte 1
Data Byte N
Data Byte N
DS3101
7.12 Reset Logic
The device has three reset controls: the RST pin, the RST bit in MCR1, and the JTAG reset pin, JTRST. The RST
pin asynchronously resets the entire device, except for the JTAG logic. When the RST pin is low, all internal
registers are reset to their default values, including those fields that latch their default values from, or based on, the
states of input pins when the RST pin goes high (such as IFCR:IFSEL[2:0]). The RST pin must be asserted once
after power-up while the external oscillator is stabilizing.
The MCR1:RST bit resets the entire device (except for the microprocessor interface, the JTAG logic, and the RST
bit itself), but when RST is active, the register fields with pin-programmed defaults do not latch their values from, or
based on, the corresponding input pins. Instead, these fields are reset to the default values that were latched when
the RST pin was last active.
Maxim recommends holding RST low while the external oscillator starts up and stabilizes. Some OCXOs take
250ms or more to start up and stabilize their output signals to valid logic levels and pulse widths. An incorrect reset
condition could result if RST is released before the oscillator has started up completely.
Important: System software must wait at least 100μs after reset (RST pin or RST bit) is deasserted before
initializing the device as described in Section 7.14.
19-4596; Rev 4; 5/09
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