MAX16060 Datasheet, PDF (8/18 Pages) Maxim Integrated Products – 1% Accurate, Quad-/Hex-/Octal-Voltage uP Supervisors

1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Pin Description (MAX16061)
PIN
NAME
FUNCTION
1
IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
2
IN5 Monitored Input Voltage 5. See Table 1 for the input voltage threshold.
3
IN6 Monitored Input Voltage 6. See Table 1 for the input voltage threshold.
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET is
asserted and the timer is cleared. The timer also clears whenever a reset is asserted or a rising or falling
edge on WDI is detected. The watchdog timer enters a startup period that allows 54s for the first transition to
4
WDI occur before a reset. Leave WDI unconnected to disable the watchdog timer.
The WDI unconnected-state detector uses a small 400nA current. Therefore, do not connect WDI to anything
that will source or sink more than 200nA. Note that the leakage current specification for most three-state
drivers exceeds 200nA.
5
GND Ground
6
V_CC Unmonitored Power-Supply Input
Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at
7
OUT4 _{IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.}
Output 5. When the voltage at IN5 falls below its threshold, OUT5 goes low and stays low until the voltage at
8
OUT5 _{IN5 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.}
Output 6. When the voltage at IN6 falls below its threshold, OUT6 goes low and stays low until the voltage at
9
OUT6 _{IN6 exceeds its threshold. The open-drain output has a 30µA internal pullup to VCC.}
10
MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset timeout
period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
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SRT
timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). For the internal timeout period of 140ms (min), connect SRT to
V_CC.
12
MARGIN
Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state), regardless of the voltage
at any monitored input.
13
OUT3
Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at
IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
14
OUT2
Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at
IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
15
OUT1
Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at
IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its respective
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RESET threshold or MR is asserted. RESET remains asserted for the reset timeout period after all monitored voltages
exceed their respective thresholds and MR is deasserted. This open-drain output has a 30µA internal pullup.
17
IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
18
IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
19
IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
20
TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to V_CC to
select 10% threshold tolerance.
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low thermal
resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
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