MAX16060 Datasheet, PDF (7/18 Pages) Maxim Integrated Products – 1% Accurate, Quad-/Hex-/Octal-Voltage uP Supervisors

1% Accurate, Quad-/Hex-/Octal-Voltage
µP Supervisors
Pin Description (MAX16060)
PIN
NAME
FUNCTION
1
IN3 Monitored Input Voltage 3. See Table 1 for the input voltage threshold.
2
IN4 Monitored Input Voltage 4. See Table 1 for the input voltage threshold.
Watchdog Timer Input. If WDI remains low or high for longer than the watchdog timeout period, RESET
is asserted. The timer clears whenever a reset is asserted or a rising or falling edge on WDI is detected.
3
WDI
The watchdog timer enters a startup period that allows 54s for the first transition to occur before a reset.
Leave WDI unconnected to disable the watchdog timer. The WDI unconnected-state detector uses a
small 400nA current. Therefore, do not connect WDI to anything that will source or sink more than
200nA. Note that the leakage current specification for most three-state drivers exceeds 200nA.
4
GND Ground
5
V_CC Unmonitored Power-Supply Input
6
OUT3 ^{Output 3. When the voltage at IN3 falls below its threshold, OUT3 goes low and stays low until the voltage at}
IN3 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
7
OUT4 ^{Output 4. When the voltage at IN4 falls below its threshold, OUT4 goes low and stays low until the voltage at}
IN4 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
8
MR
Active-Low Manual Reset Input. Pull MR low to assert RESET low. RESET remains low for the reset
timeout period after MR is deasserted. MR is pulled up to V_CC through a 20kΩ resistor.
Set Reset Timeout Input. Connect a capacitor from SRT to GND to set the reset timeout period. The reset
9
SRT
timeout period can be calculated as follows:
Reset Timeout (s) = 2.06 x 10⁶ (Ω) x C_SRT (F). For the internal timeout period of 140ms (min), connect
SRT to V_CC.
10
MARGIN ^{Active-Low Manual Deassert Input. Pull MARGIN low to deassert all outputs (go into high state),}
regardless of the voltage at any monitored input.
11
OUT2 ^{Output 2. When the voltage at IN2 falls below its threshold, OUT2 goes low and stays low until the voltage at}
IN2 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
12
OUT1 ^{Output 1. When the voltage at IN1 falls below its threshold, OUT1 goes low and stays low until the voltage at}
IN1 exceeds its threshold. The open-drain output has a 30µA internal pullup to V_CC.
Active-Low Reset Output. RESET asserts low when any of the monitored voltages falls below its
13
RESET
respective threshold or MR is asserted. RESET remains asserted for the reset timeout period after all
monitored voltages exceed their respective thresholds and MR is deasserted. This open-drain output
has a 30µA internal pullup.
14
IN1 Monitored Input Voltage 1. See Table 1 for the input voltage threshold.
15
IN2 Monitored Input Voltage 2. See Table 1 for the input voltage threshold.
16
TOL
Threshold Tolerance Input. Connect TOL to GND to select 5% threshold tolerance. Connect TOL to V_CC
to select 10% threshold tolerance.
—
EP
Exposed Pad. EP is internally connected to GND. Connect EP to the ground plane to provide a low
thermal resistance path from the IC junction to the PCB. Do not use as the electrical connection to GND.
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