MAX1245 Datasheet, PDF (8/20 Pages) Maxim Integrated Products – +2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________Detailed Description
The MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (µPs). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor CHOLD. The acqui-
sition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition inter-
val, the T/H switch opens, retaining charge on CHOLD as a
sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input, IN+, to the
negative input, IN- (In single-ended mode, IN- is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(VIN+) -
(VIN-)] from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-| is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ = 9 x (RS + RIN) x 16pF
CS ¹⁸
SCLK ¹⁹
DIN ¹⁷
INPUT
SHIFT
REGISTER
SHDN ¹⁰
CONTROL
LOGIC
INT
CLOCK
CH0 ¹
CH1 ²
CH2 ³
CH3 ⁴
CH4 ⁵
CH5 ⁶
CH6 ⁷
CH7 ⁸
COM ⁹
VREF ¹¹
ANALOG
INPUT
MUX
T/H
MAX1245
OUTPUT
SHIFT
REGISTER
CLOCK
IN
12-BIT
SAR
ADC
OUT
REF
15
DOUT
16
SSTRB
12, 20
VDD
14
DGND
13 _AGND
12-BIT CAPACITIVE DAC
VREF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
INPUT
MUX
CHOLD
–+
ZERO
COMPARATOR
16pF
CSWITCH
TRACK
RIN
12k
HOLD
T/H
SWITCH
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
Figure 3. Block Diagram
Figure 4. Equivalent Input Circuit
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