MAX1245 Datasheet, PDF (13/20 Pages) Maxim Integrated Products – +2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
CS
SCLK
1 2 345678
9 10 11 12
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
START
tCONV
A/D STATE
ACQUISITION CONVERSION
IDLE
2.0µs
7.5µs MAX
(SCLK = 1.5MHz)(SHDN = FLOAT)
Figure 9. Internal Clock Mode Timing
B11
MSB
B10
B9
IDLE
18 19 20 21 22 23 24
B2
B1
B0 ^{FILLED WITH}
LSB ZEROS
CS • • •
tCONV
tCSH
tCSS
tSCK
SSTRB • • •
tSSTRB
SCLK • • •
tDO
PD0 CLOCK IN
DOUT • • •
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 10. Internal Clock Mode SSTRB Detailed Timing
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provid-
ed that the minimum acquisition time, tACQ, is kept
above 2.0µs.
Data Framing
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V_DD is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated,
and a new one is started.
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