MAX1245 Datasheet, PDF (11/20 Pages) Maxim Integrated Products – +2.375V, Low-Power, 8-Channel, Serial 12-Bit ADC

+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
perform a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the 12-bit
conversion result). See Figure 17 for MAX1245 QSPI
connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 1.5MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of idle time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar inputs, the output is two’s-com-
plement (Figure 15). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock Modes
The MAX1245 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX1245. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7–10 show the
timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version. SSTRB pulses high for one clock period after
the control byte’s last bit. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
CS
SCLK
1
tACQ
4
8
DIN
SSTRB
DOUT
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1
PD0
START
RB1
A/D STATE
ACQUISITION
IDLE
2.0µs
(SCLK = 1.5MHz)
12
16
20
24
RB2
RB3
B11
MSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0 ^{FILLED WITH}
LSB ZEROS
CONVERSION
IDLE
Figure 6. 24-Clock External-Clock-Mode Conversion Timing (Microwire and SPI Compatible, QSPI Compatible with fCLK ≤ 1.5MHz)
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