MAX1161 Datasheet, PDF (8/8 Pages) Maxim Integrated Products – 10-Bit, 40Msps, TTL-Output ADC

10-Bit, 40Msps, TTL-Output ADC
Table 2. Output Data Information
ANALOG
INPUT
> +2V + 1/2LSB
+2V - 1LSB
0.0V
-2V + 1LSB
OVERRANGE
D10
1
0
0
0
OUTPUT CODE
D9–D0
11 1111 1111
11 1111 111Ø
ØØ ØØØØ ØØØØ
00 0000 000Ø
< 2V
0
00 0000 0000
(Ø indicates the flickering bit between logic 0 and 1.)
Clock Input
The MAX1161 is driven from a single-ended TTL input
(CLK). The CLK pulse width (t_pwH) must be kept
between 10ns and 300ns to ensure proper operation of
the internal track/hold amplifier (Figure 1a). When oper-
ating the MAX1161 at sampling rates above 3Msps, it is
recommended that the clock input duty cycle be kept
at 50% to optimize performance (Figure 4). The analog
input signal is latched on the rising edge of CLK.
The clock input must be driven from fast TTL logic (VIH
≤ 4.5V, t_RISE <6ns). In the event the clock is driven from
a high current source, use a 100Ω resistor (R5) in
series to limit current to approximately 45mA.
Digital Outputs
The format of the output data (D0–D9) is straight binary
(Table 2). The outputs are latched on the rising edge of
CLK with a propagation delay typically at 14ns. There is
a one-clock-cycle latency between CLK and the valid
output data (Figure 1a).
The digital outputs’ rise and fall times are not symmetri-
cal. Typical propagation delay is 14ns for the rise time
and 6ns for the fall time (Figure 5). The nonsymmetrical
rise and fall times create approximately 8ns of invalid
data.
Overrange Output
The overrange output (D10) is an indication that the
analog input signal has exceeded the positive full-scale
input voltage by 1LSB. When this condition occurs, D10
will switch to logic 1. All other data outputs (D0–D9) will
remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the MAX1161
in higher-resolution systems.
Evaluation Board
The MAX1160 EV kit is available to help designers
demonstrate the MAX1160 or MAX1161’s full perfor-
mance. This board includes a reference circuit, clock-
driver circuit, output data latches, and an on-board
reconstruction of the digital data. A separate data sheet
describing the operation of this board is also available.
Contact the factory for price and availability.
59
57
55
53
51
DUTY CYCLE = ^tpwL
t_pwH
49
t_pwL
47
t_pwH
45
43
25 30 35 40 45 50 55 60 65 70 75
DUTY CYCLE OF POSITIVE CLOCK PULSE (°C)
Figure 4. SNR vs. Clock Duty Cycle
N
N+1
CLK IN _2.4V
6ns
typ
3.5V
DATA _2.4V
OUT
(ACTUAL) 0.8V
0.5V
INVALID
(N - 2) ^DATA
t_pd1
14ns typ
(N - 1)
DATA OUT _{(N - 2)} INVALID
(EQUIVALENT)
DATA
(N - 1)
Figure 5. Digital Output Characteristics
t_RISE
6ns
INVALID
DATA
N
INVALID
N
DATA
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 [phone]
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.