MAX1161 Datasheet, PDF (6/8 Pages) Maxim Integrated Products – 10-Bit, 40Msps, TTL-Output ADC

10-Bit, 40Msps, TTL-Output ADC
N
t_pwH
CLK
OUTPUT
DATA
N-2
N+1
t_pwL
t_d
N-1
N+2
DATA VALID
N
DATA VALID
N+1
CLK
OUTPUT
DATA
t_d
DATA VALID
Figure 1a. Timing Diagram
Figure 1b. Single-Event Clock
Table 1. Timing Parameters
PARAMETER
t_d
t_pwH
t_pwL
DESCRIPTION
MIN
CLK to Data Valid Propagation Delay
CLK High Pulse Width
10
CLK Low Pulse Width
10
TYP
MAX
14
18
300
UNITS
ns
ns
ns
Connect a Schottky or hot carrier diode between AGND
and V_EE. The use of separate power supplies between
V_CC and DV_CC is not recommended due to potential
power-supply-sequencing latchup conditions. For opti-
mum performance, use the recommended circuit
shown in Figure 2.
Voltage Reference
The MAX1161 requires the use of two voltage refer-
ences: VFT and VFB. VFT is the force for the top of the
voltage-reference ladder (typically +2.5V); VFB (typical-
ly -2.5V) is the force for the bottom of the voltage-
reference ladder. Both voltages are applied across an
800Ω internal reference-ladder resistance. The +2.5V
voltage source for reference VFT must be current limited
to 20mA (max) if a different driving circuit is used in
place of the recommended reference circuit shown in
Figures 2 and 3. In addition, there are three reference-
ladder taps (VST, VRM, and VSB). VST is the sense for
the top of the reference ladder (+2V), VRM is the mid-
point of the ladder (typically 0V), and VSB is the sense
for the bottom of the reference ladder (-2V). The volt-
ages at VST and VSB are the device’s true full-scale
input voltages when VFT and VFB are driven to the rec-
ommended voltages (+2.5V and -2.5V, respectively).
These points should be used to monitor the device’s
actual full-scale input range. When not being used, a
decoupling capacitor of 0.01µF (chip carrier preferred)
connected to AGND from each tap is recommended to
minimize high-frequency noise injection.
Figure 2 shows an example of a recommended refer-
ence-driver circuit. IC1 (MAX6225) is a +2.5V reference
with 0.2% accuracy. Potentiometer R1 is 10kΩ and sup-
ports a minimum adjustable range of 0.6%. Use an
OP07 or equivalent device for IC2. R2 and R3 must be
matched to within 0.1% with good TC tracking to main-
tain 0.3LSB matching between VFT and VFB. If 0.1%
matching is not met, then R4 can be used to adjust the
VFB voltage to the desired level. Adjust VFT and VFB
such that VST and VSB are exactly +2V and -2V,
respectively.
The analog input range scales proportionally with respect
to the reference voltage if a different input range is
required. The maximum scaling factor for device opera-
tion is ±20% of the recommended reference voltages of
VFT and VFB. However, because the device is laser
trimmed to optimize performance with ±2.5V references,
its accuracy degrades if operated beyond a ±2% range.
The following errors are defined:
+FS error = top of ladder offset voltage
= ∆ (+FS - VST + 1LSB)
-FS error = bottom of ladder offset voltage
= ∆ (-FS - VSB - 1LSB)
where the +FS (full-scale) input voltage is defined as the
output transition between 11 1111 1110 and 11 1111 1111,
and the -FS input voltage is defined as the output transi-
tion between 00 0000 0000 and 00 0000 0001 (Table 2).
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