MAX1161 Datasheet, PDF (5/8 Pages) Maxim Integrated Products – 10-Bit, 40Msps, TTL-Output ADC

10-Bit, 40Msps, TTL-Output ADC
__________________________________________Typical Operating Characteristics
(T_A = +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs.
INPUT FREQUENCY
80
f_S = 40Msps
70
SIGNAL-TO-NOISE vs.
INPUT FREQUENCY
80
f_S = 40Msps
70
SIGNAL-TO-NOISE AND DISTORTION
vs. INPUT FREQUENCY
80
f_S = 40Msps
70
60
60
60
50
50
50
40
40
40
30
30
30
20
1
10
100
INPUT FREQUENCY (MHz)
20
20
1
10
100
1
10
100
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
SNR, THD, SINAD vs.
SAMPLE RATE
80
f_IN = 1MHz
70
SNR
60
50
SINAD
THD
40
30
20
1
10
100
SAMPLE RATE (Msps)
SNR, THD, SINAD vs.
TEMPERATURE
65
60
SNR
THD
55
SINAD
50
45
f_S = 40Msps
f_IN = 1MHz
40
-25
0
25
50
75
TEMPERATURE (°C)
SPECTRAL RESPONSE
0
f_S = 40Msps
f_IN = 1MHz
-30
-60
-90
-120
0
2
4
6
8
10
INPUT FREQUENCY (MHz)
_______________Detailed Description
The MAX1161 requires few external components to
achieve the stated operation and performance. Figure 2
shows the typical interface requirements when using the
MAX1161 in normal circuit operation. The following sec-
tion provides a description of the pin functions, and out-
lines critical performance criteria to consider for
achieving optimal device performance.
Power Supplies and Grounding
The MAX1161 requires -5.2V and +5V analog supply
voltages. The +5V supply is common to analog V_CC and
digital DV_CC. A ferrite bead in series with each supply
line reduces the transient noise injected into the analog
V_CC. These beads should be connected as close to the
device as possible. The connection between the beads
and the MAX1161 should not be shared with any other
device. Bypass each power-supply pin as close to the
device as possible. Use 0.1µF for V_EE and V_CC, and
0.01µF for DV_CC (chip capacitors are recommended).
The MAX1161 has two grounds: AGND and DGND.
These internal grounds are isolated on the device. Use
ground planes for optimum device performance.
Use DGND for the DV_CC return path (typically 40mA)
and for the return path for all digital output logic inter-
faces. Separate AGND and DGND from each other,
connecting them together only through a ferrite bead at
the device.
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