MAX1161 Datasheet, PDF (4/8 Pages) Maxim Integrated Products – 10-Bit, 40Msps, TTL-Output ADC

10-Bit, 40Msps, TTL-Output ADC
ELECTRICAL CHARACTERISTICS (continued)
(V_CC = +5.0V, V_EE = -5.2V, DV_CC = +5.0V, V_IN = ±2.0V, VSB = -2.0V, VST = +2.0V, f_CLK = 40MHz, 50% clock duty cycle,
T_A = T_MIN to T_MAX, unless otherwise noted.)
PARAMETER
CONDITIONS
TEST
LEVEL
MAX1161A
MIN TYP MAX
MAX1161B
MIN TYP MAX
UNITS
DIGITAL INPUTS
Logic 1 Voltage
V
2.4
4.5 2.4
4.0
V
Logic 0 Voltage
V
0.8
0.8
V
Maximum Input
Current Low
T_A = +25°C
IV
0 5 20 0 5 20 µA
Maximum Input
Current High
T_A = +25°C
Pulse Width Low (CLK)
Pulse Width High (CLK)
DIGITAL OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
POWER-SUPPLY REQUIREMENTS
Voltages
Currents
Power Dissipation
V_CC
DV_CC
-V_EE
I_CC
DI_CC
-I_EE
Power-Supply Rejection V_CC = 5V ±0.25V, V_EE = -5.2V ±0.25V
IV
0 5 20 0 5 20 µA
IV
10
IV
10
10
300 10
ns
300 ns
IV 2.4
IV
2.4
0.6
V
0.6
V
IV 4.75
5.25 4.75
5.25
IV 4.75 5.0 5.25 4.75 5.0 5.25 V
IV -4.95 -5.2 -5.45 -4.95 -5.2 -5.45
VI
118 145
118 145
VI
40 55
40 55 mA
VI
40 57
40 57
VI
1.0 1.3
1.0 1.3
W
V
1.0
1.0
LSB
TEST LEVEL CODES
All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The
Test Level column indicates the specific device testing actually per-
formed during production and Quality Assurance inspection. Any
blank section in the data column indicates that the specification is
not tested at the specified condition.
Unless otherwise noted, all tests are pulsed; therefore, Tj = TC = TA.
TEST LEVEL
I
II
III
IV
V
VI
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25°C, and sample tested at the specified
temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25°C. Parameter is guaranteed over specified
temperature range.
______________________________________________________________Pin Description
PIN
1, 13
2
3–10
11
12
14, 28
15
16, 27
NAME
DGND
D0
D1–D8
D9
D10
DV_CC
CLK
V_EE
FUNCTION
Digital Ground
TTL Output (LSB)
TTL Outputs
TTL Output (MSB)
TTL Output Overrange
+5V Supply (digital)
Clock
-5.2V Supply (analog)
PIN
17, 26
18, 25
19
20
21
22
23
24
NAME
AGND
V_CC
VFT
VST
VIN
VRM
VSB
VFB
FUNCTION
Analog Ground
+5V Supply (analog)
Force for Top of Reference Ladder
Sense for Top of Reference Ladder
Analog Input
Middle of Voltage Reference Ladder
Sense for Bottom of Reference Ladder
Force for Bottom of Reference Ladder
4 _______________________________________________________________________________________