MAX11329 Datasheet, PDF (8/37 Pages) Maxim Integrated Products – 3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access

MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)
(V_DD = 2.35V to 3.6V, V_OVDD = 1.5V to 3.6V, f_SAMPLE = 3Msps, f_SCLK = 48MHz, 50% duty cycle, V_REF+ = V_DD, T_A = -40NC to +125NC,
unless otherwise noted. Typical values are at T_A = +25NC.) (Note 2)
PARAMETER
SCLK Rise to DIN Hold
CS Fall to SCLK Fall Setup
SCLK Fall to CS Fall Hold
CNVST Pulse Width
CS or CNVST Rise to EOC Low
(Note 7)
CS Pulse Width
SYMBOL
CONDITIONS
t_DH
t_CSS
t_CSH
t_CSW
See Figure 6
t_{CNV_INT} See Figure 7, f_SAMPLE = 3Msps
t_CSBW
MIN TYP MAX UNITS
1
ns
4
ns
1
ns
5
ns
1.7
2.4
Fs
5
ns
Note 2: Limits are 100% production tested at T_A = +25NC. Limits over the operating temperature range are guaranteed by design.
Parts are tested with MUX externally connected to the ADC input.
Note 3: Channel ID disabled.
Note 4: Tested in single-ended mode.
Note 5: Offset nulled.
Note 6: Line rejection D(D_OUT) with V_DD = 2.35V to 3.6V and V_REF+ = 2.35V.
Note 7: Tested and guaranteed with fully differential input.
Note 8: Conversion time is defined as the number of clock cycles multiplied by the clock period with a 50% duty cycle.
Maximum conversion time: 1.91Fs + N x 16 x t_{OSC_MAX}
t_{OSC_MAX} = 29.4ns, t_{OSC_TYP} = 25ns.
Note 9: The operational input voltage range for each individual input of a differentially configured pair is from V_DD to GND. The
operational input voltage difference is from -V_REF+/2 to +V_REF+/2 or -V_REF+ to +V_REF+.
Note 10: See Figure 3 (Equivalent Input Circuit).
Note 11: Guaranteed by characterization.
CS
tCSS
tCH
SCLK
1ST
CLOCK
tDH
tDS
DIN
tDOE
DOUT
tCP
tDOT
tCSBW
tCSH
16TH
CLOCK
tDOD
Figure 1. Detailed Serial-Interface Timing Diagram
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