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MAX11329 Datasheet, PDF (6/37 Pages) Maxim Integrated Products – 3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access
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MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
ELECTRICAL CHARACTERISTICS (MAX11329/MAX11330) (continued)
(VDD = 2.35V to 3.6V, VOVDD = 1.5V to 3.6V, fSAMPLE = 3Msps, fSCLK = 48MHz, 50% duty cycle, VREF+ = VDD, TA = -40NC to +125NC,
unless otherwise noted. Typical values are at TA = +25NC.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Crosstalk
-0.5dB below full-scale of 99.2432kHz
sine-wave input to the channel being
sampled; apply full-scale 69.2139kHz sine
-88
dB
wave signal to all 15 nonselected
input channels
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
tPU
tACQ
tCONV
fSCLK
Conversion cycle, external clock
Internally clocked (Note 8)
Externally clocked, fSCLK = 48MHz,
16 cycles (Note 8)
RMS
VINA
Unipolar (single-ended and pseudo
differential)
RANGE bit set to 0
Bipolar (Note 9)
RANGE bit set to 1
Absolute Input Voltage Range
AIN+, AIN- relative to GND
Static Input Leakage Current
IILA
Input Capacitance
CAIN
EXTERNAL REFERENCE INPUT
REF- Input Voltage Range
REF+ Input Voltage Range
VREF-
VREF+
REF+ Input Current
IREF+
DIGITAL INPUTS (SCLK, DIN, CS, CNVST)
Input Voltage Low
VIL
VAIN_ = VDD, GND
During acquisition time,
RANGE bit = 0 (Note 10)
During acquisition time,
RANGE bit = 1 (Note 10)
VREF+ = 2.5V, fSAMPLE = 3Msps
VREF+ = 2.5V, fSAMPLE = 0Msps
Input Voltage High
VIH
52
2.1
333
0.48
8
30
2 Cycles
ns
µs
ns
48
MHz
ns
ps
0
VREF+
-VREF+
/2
+VREF+
V
/2
-VREF+
-0.1
+VREF+
VREF+
+ 0.1
V
-0.1 ±1.5
FA
15
pF
7.5
-0.3
+1
V
1
VDD
+50mV
V
110
FA
0.1
FA
VOVDD
O 0.75
VOVDD
O 0.25
V
V
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