MAX11329 Datasheet, PDF (26/37 Pages) Maxim Integrated Products – 3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access

MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Table 6. ADC Configuration Register (continued)
BIT NAME
NAVG[1:0]
NSCAN[1:0]
SPM[1:0]
ECHO
—
BIT
DEFAULT
STATE
FUNCTION
Valid for internal clock mode only.
AVGON NAVG1 NAVG0
FUNCTION
0
X
X
Performs 1 conversion for each requested
result.
8:7
00
1
0
1
0
0
Performs 4 conversions and returns the
average for each requested result.
1
Performs 8 conversions and returns the
average for each requested result.
1
1
0
Performs 16 conversions and returns the
average for each requested result.
1
1
1
Performs 32 conversions and returns the
average for each requested result.
Scans channel N and returns 4, 8, 12, or 16 results. Valid for repeat mode only.
NSCAN1
NSCAN0
FUNCTION
0
6:5
00
0
0
Scans channel N and returns 4 results.
1
Scans channel N and returns 8 results.
1
0
Scans channel N and returns 12 results.
1
1
Scans channel N and returns 16 results.
Static power-down modes
SPM1 SPM0 MODE
FUNCTION
0
0
Normal All circuitry is fully powered up at all times.
4:3
00
0
1
Full
All circuitry is powered down. The information
Shutdown in the registers is retained.
1
0
Partial
Shutdown
All circuitry is powered down except for
the reference and reference buffer. The
information in the registers is retained.
1
1
—
Reserved
Set to 0 to disable the instruction echo on DOUT.
2
0
Set to 1 to echo back the DIN instruction given at time = n onto the DOUT line at
time = n + 1. It takes 1 full cycle for the echoing to begin (Figure 8).
1:0
0
Unused
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