MAX11201 Datasheet, PDF (8/14 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Pin Configuration
TOP VIEW
+
GND 1
REFP 2
REFN 3
MAX11201
AINN 4
AINP 5
10 CLK
9 SCLK
8 RDY/DOUT
7 DVDD
6 AVDD
µMAX
Pin Description
PIN
NAME
FUNCTION
1
GND
Ground. Ground reference for analog and digital circuitry.
2
REFP
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a volt-
age between AVDD and GND.
3
REFN
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a
voltage between AVDD and GND.
4
AINN
Negative Fully Differential Analog Input
5
AINP
Positive Fully Differential Analog Input
6
AVDD
Analog Supply Voltage. Connect a supply voltage between +2.7V to +3.6V with respect to GND.
7
DVDD Digital Supply Voltage. Connect a digital supply voltage between +1.7V to +3.6V with respect to GND.
Data Ready Output/Serial Data Output. This output serves a dual function. In addition to the serial data
8
RDY/DOUT output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/
DOUT changes on the rising edge of SCLK.
9
SCLK
Serial Clock Input. Apply an external serial clock to SCLK.
10
CLK
External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock.
Use a 2.4576MHz oscillator (MAX11201A) or a 2.25275MHz oscillator (MAX11201B).
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