MAX11201 Datasheet, PDF (10/14 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Reference
The MAX11201 provides differential inputs REFP and
REFN for an external reference voltage. Connect the
external reference directly across the REFP and REFN to
obtain the differential reference voltage. The common-
mode voltage range for VREFP and VREFN is between 0
and VAVDD. The differential voltage range for REFP and
REFN is 1.25V to VAVDD.
Digital Filter
The MAX11201 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC⁴ (sinx/x)⁴ response. When the device is
operating in single-cycle conversion mode, the filter is
reset at the end of the conversion cycle. When operat-
ing in continuous conversion latent mode, the filter is not
reset. The SINC⁴ filter has a -3dB frequency equal to
24% of the data rate.
Data Output
The data output is clocked out on RDY/DOUT. D23 is
the MSB and D0 is the LSB. The data format is always
two’s complement. In two’s complement format, the most
negative value is 0x800000 (VAINP - VAINN = -VREF), the
midscale value is 0x000000 (AINP - AINN = 0), and the
most positive value is 0x7FFFFF (VAINP - VAINN = VREF).
Any input exceeding the available input range is limited
to the minimum or maximum data value.
Table 1. Output Data Format
INPUT VOLTAGE
VAINP - VAINN
≥ VREF
V_REF
x
_1−

1
2 ²³
−


1
V_REF
2²³ − 1
0
−V_REF
2²³ − 1
DIGITAL OUTPUT CODE
0x7FFFFF
0x7FFFFE
0x000001
0x000000
0xFFFFFF
V_REF
x
_1−

2
1
23
−


1
≤ -VREF
0x800001
0x800000
Serial-Digital Interface
The MAX11201 communicates through a 2-wire inter-
face, with a clock input and data output. The output
rate is predetermined based on the package option
(MAX11201A at 120sps and MAX11201B at 13.75sps).
2-Wire Interface
The MAX11201 is compatible with the 2-wire interface
and uses SCLK and RDY/DOUT for serial communica-
tions. In this mode, all controls are implemented by tim-
ing the high or low phase of the SCLK. The 2-wire serial
interface only allows for data to be read out through the
RDY/DOUT output. Supply the serial clock to SCLK to
shift the conversion data out.
The RDY/DOUT is used to signal data ready, as well as
reading the data out when SCLK pulses are applied.
RDY/DOUT is high by default. The MAX11201 pulls
RDY/DOUT low when data is available at the end of con-
version, and stays low until clock pulses are applied at
the SCLK input. On applying the clock pulses at SCLK,
the RDY/DOUT outputs the conversion data on every
SCLK positive edge. To monitor data availability, pull
RDY/DOUT high after reading the 24 bits of data by sup-
plying a 25th SCLK pulse.
The different operational modes using this 2-wire inter-
face are described in the following sections.
Data Read Following Every Conversion
The MAX11201 indicates conversion data availability, as
well as the retrieval of data through the RDY/DOUT out-
put. The RDY/DOUT output idles at the value of the last
bit read unless a 25th SCLK pulse is provided, causing
RDY/DOUT to idle high.
The timing diagram for the data read is shown in
Figure 1. Once a low is detected on RDY/DOUT, clock
pulses at SCLK clock out the data. Data is shifted out
MSB first and is in binary two’s complement format.
Once all the data has been shifted out, a 25th SCLK is
required to pull the RDY/DOUT output back to the idle
high state. See Figure 2.
If the data is not read before the next conversion data is
updated, the old data is lost, as the new data overwrites
the old value.
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