MAX11201 Datasheet, PDF (12/14 Pages) Maxim Integrated Products – 24-Bit, Single-Channel, Ultra-Low-Power, Delta Sigma ADC with 2-Wire Serial Interface

24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
SCLK
1
2
3
RDY/DOUT
CONVERSION IS DONE
DATA IS AVAILABLE
D23
D22
CALIBRATION STARTS ON 26TH SCLK
24
25
26
25TH SCLK PULLS
RDY/DOUT HIGH
D0
1
2
D23 D22
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t8
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
SCLK
RDY/DOUT
CONVERSION IS DONE
DATA IS AVAILABLE
1
2
3
t9
t10
D23
D22
DEVICE ENTERS
SLEEP MODE
DEVICE EXITS OUT
SLEEP MODE
24
SLEEP
MODE
1
2
D0
D23
D22
CONVERSION IS DONE
DATA IS AVAILABLE
t11
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single Conversion Timing
Single-Conversion Mode
with Self-Calibration at Wake-Up
The MAX11201 can be put in self-calibration mode imme-
diately after wake-up from sleep mode. Self-calibration at
wake-up helps to compensate for temperature or supply
changes if the device is shut down for extensive periods.
To automatically start self-calibration at the end of sleep
mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th
SCLK, keep it high for as long as shutdown is desired.
Once SCLK is pulled back low, the device automatically
performs a self-calibration and, when the data is ready,
the RDY/DOUT output goes low. See Figure 5. This also
achieves the purpose of single conversions with self-
calibration.
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