DS4510 Datasheet, PDF(8/12 Page) Maxim Integrated Products – CPU Supervisor with Nonvolatile Memory and Programmable I/O

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DS4510 Datasheet, PDF (8/12 Pages) Maxim Integrated Products – CPU Supervisor with Nonvolatile Memory and Programmable I/O

◁

CPU Supervisor with Nonvolatile Memory and

Programmable I/O

REGISTER

REGISTER

NAME

LOCATION

(HEX)

Bit 7

User

EEPROM

00-3F

EE

Reserved

40-EF

n/a

Pullup

Enable

F0

SEE

RST Delay

F1

SEE

User SEE

F2

SEE

User SEE

F3

SEE

I/O3

Control

F4

SEE

Bit 6

EE

n/a

SEE

SEE

SEE

SEE

SEE

REGISTER BIT NAMES

Bit5

Bit 4

Bit 3

Bit 2

EE

EE

EE

EE

n/a

n/a

n/a

n/a

SEE

SEE

I/O3

pullup

I/O2

pullup

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

SEE

Bit 1

EE

n/a

I/O1

pullup

TD1

SEE

SEE

SEE

Bit 0

FACTORY OR

POWER-ON

DEFAULT

(BIN)

EE

00000000

n/a

I/O0

pullup

TD0

SEE

SEE

n/a

00000000

00000011

00000000

00000000

I/O3

00000001

I/O2

F5

Control

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O2

00000001

I/O1

F6

Control

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O1

00000001

I/O0

F7

Control

SEE

SEE

SEE

SEE

SEE

SEE

SEE

I/O0

00000001

I/O Status

F8

0

0

0

0

I/O3

I/O2

I/O1

I/O0

n/a

Status Status Status Status

Config

F9

ready

User SRAM FA-FF

SRAM

Figure 4. Register Bit Names

trip point

SRAM

reset

status

SRAM

SEE

SRAM

SWRST

SRAM

0

SRAM

0

SRAM

0

SRAM

XXX00000

00000000

I2C Definitions

The following terminology is commonly used to

describe I2C data transfers.

Master Device: The master device controls the slave

devices on the bus. The master device generates SCL

clock pulses, start, and stop conditions.

Slave Devices: Slave devices send and receive data

at the masterâs request.

Bus Idle or Not Busy: Time between stop and start

conditions when both SDA and SCL are inactive and in

their logic-high states. When the bus is idle it often initi-

ates a low-power mode for slave devices.

Start Condition: A start condition is generated by the

master to initiate a new data transfer with a slave.

Transitioning SDA from high to low while SCL remains

high generates a start condition. See the timing dia-

gram for applicable timing.

Stop Condition: A stop condition is generated by the

master to end a data transfer with a slave. Transitioning

SDA from low to high while SCL remains high gener-

ates a stop condition. See the I2C Timing Diagram for

applicable timing.

Repeated Start Condition: The master can use a

repeated start condition at the end of one data transfer

to indicate that it will immediately initiate a new data

transfer following the current one. Repeated starts are

commonly used during read operations to identify a

specific memory address to begin a data transfer. A

repeated start condition is issued identically to a nor-

mal start condition. See the I2C Timing Diagram for

applicable timing.

Bit Write: Transitions of SDA must occur during the low

state of SCL. The data on SDA must remain valid and

unchanged during the entire high pulse of SCL (see

Figure 5) plus the setup and hold-time requirements.

Data is shifted into the device during the rising edge of

the SCL.

Bit Read: At the end a write operation, the master must

release the SDA bus line for the proper amount of setup

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