DS4510 Datasheet, PDF (7/12 Pages) Maxim Integrated Products – CPU Supervisor with Nonvolatile Memory and Programmable I/O

CPU Supervisor with Nonvolatile Memory and
Programmable I/O
transistors. Read the I/O status register (F8h) to deter-
mine the logic levels present at the I/O pins.
User Memory
Three types of memory are present in the DS4510
(EEPROM, SEEPROM, and SRAM). The main user
memory is 64 bytes of EEPROM starting at address
00h. This memory is not SRAM shadowed, so all writes
to these locations result in EEPROM write cycles
regardless of the state of the SEE bit. Additional memo-
ry for storing application data includes 6 bytes of SRAM
(FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer
to the register memory map (Figure 3) for register
addresses and memory types. Figure 4 shows the bit
names for the memory-mapped I/O bytes and their fac-
tory default values.
The higher-order bits of the I/O registers that are not
used, such as the four most significant bits of the
pullup-enable byte (address F0h), can be used as
additional memory. It is the responsibility of the appli-
cation to ensure that writes to these bytes do not
adversely affect bits controlling special functions of the
DS4510.
V_{CCTP (MIN)}
t_R
V_{CCTP (MAX)}
V_CCTP
t_RPU
V_OH
V_{CCTP (MAX)}
V_CCTP
t_F
V_{CCTP (MIN)}
t_RPD
V_OL
Figure 1. CPU Supervisor Power-Up and Power-Down Timing
REGISTER ADDRESS (HEX)
MEMORY TYPE
F8
I/O STATUS
SRAM
REGISTER NAME
Figure 2. How to Read the Memory Map
00
EE 01
EE 02
EE 03
EE 04
EE 05
EE 06
EE 07
EE
USER BYTE
08
USER BYTE
EE 09
User byte
EE 0A
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
EE 0B
EE 0C
EE 0D
EE 0E
EE 0F
EE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
10
EE 11
EE 12
EE 13
EE 14
EE 15
EE 16
EE 17
EE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
18
EE 19
EE 1A
EE 1B
EE 1C
EE 1D
EE 1E
EE 1F
EE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
20
EE 21
EE 22
EE 23
EE 24
EE 25
EE 26
EE 27
EE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
28
EE 29
EE 2A
EE 2B
EE 2C
EE 2D
EE 2E
EE 2F
EE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
30
EE 31
EE 32
EE 33
EE 34
EE 35
EE 36
EE 37
EE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
38
EE 39
EE 3A
EE 3B
EE 3C
EE 3D
EE 3E
EE 3F
EE
USER BYTE
40
USER BYTE
41
USER BYTE
42
USER BYTE
43
USER BYTE
44
USER BYTE
45
USER BYTE
46
USER BYTE
47
RESERVED
E8
E9
EA
F0
SEE F1
SEE F2
PULLUP ENABLE RESET DELAY
USER BYTE
F8
SRAM F9
SRAM FA
I/O STATUS
CONFIG
USER BYTE
EB
SEE F3
USER BYTE
SRAM FB
USER BYTE
EC
ED
EE
EF
SEE F4
SEE F5
SEE F6
SEE F7
SEE
I/O₃ CONTROL
I/O₂ CONTROL
I/O₁ CONTROL
I/O₀ CONTROL
SRAM FC
SRAM FD
SRAM FE
SRAM FF
SRAM
USER BYTE
USER BYTE
USER BYTE
USER BYTE
*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.
Figure 3. Register Memory Map
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