DS4510 Datasheet, PDF(6/12 Page) Maxim Integrated Products – CPU Supervisor with Nonvolatile Memory and Programmable I/O

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DS4510 Datasheet, PDF (6/12 Pages) Maxim Integrated Products – CPU Supervisor with Nonvolatile Memory and Programmable I/O

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CPU Supervisor with Nonvolatile Memory and

Programmable I/O

Functional Diagram

SDA

SCL

2-WIRE

INTERFACE

VCC

GND

EEPROM

64 BYTES

USER

MEMORY

VCC

DS4510

INTERNAL

VOLTAGE

REFERENCE

PROGRAMMABLE

RESET

TIMER

4 BIDIRECTIONAL

NONVOLATILE I/O LATCHES

PULLUP ENABLE (F0h)

I/OX CONTROL (F4h-F7h)

I/O STATUS (F8h)

VCC

RST

4 NV

I/O PINS

Detailed Description

The DS4510 contains a CPU supervisor, four program-

mable I/O pins, and a 64-byte EEPROM memory. All

functions are configurable or controllable through an

industry-standard I2C-compatible bus. DS4510 NV reg-

isters that are likely to require frequent modification are

implemented using SRAM-shadowed EEPROM (SEEP-

ROM) memory. This memory is configurable to act as

volatile SRAM or NV EEPROM by adjusting the SEE bit

in the Config register. Configuring the SEEPROM as

SRAM eliminates the EEPROM write time and allows

infinite write cycles to these registers. Configuring the

registers as EEPROM allows the application to change

the power-on values that are recalled during power-up.

Programmable CPU Supervisor

The timeout period is adjusted by writing the reset

delay register (SEEPROM). The delay for each setting

is shown in the CPU Supervisor AC Electrical

Characteristics. If the SEE bit is set, changes are writ-

ten to SRAM. On power-up the last value written to the

EEPROM is recalled. The I2C bus is also used to acti-

vate the RST by setting the SWRST bit in the Config

timeout period. The Config register also contains the

ready, trip point, and reset status bits. The ready bit

determines if the power-on reset level of the DS4510 is

surpassed by VCC. The trip point bit determines if VCC

is above VCCTP, and the reset status bit is set if RST is

in its active state.

Note: The RST pin is an open-drain output, therefore an

external pullup resistor must be used to realize high

logic levels.

Programmable NV Digital I/O Pins

Each programmable I/OX pin contains an input, open-

collector output, and a selectable internal pullup resis-

tor. The DS4510 stores changes to the I/OX pin in

SEEPROM memory. Using the SEEPROM as SRAM is

conducive to applications such as I/O expansion that

generally require fast access times and frequent modi-

fication of the I/OX pin. Configuring the SEEPROM to

behave as EEPROM allows the modification of the

power-on state of the I/OX pin. During power-up the

I/OX pins are high impedance until VCC exceeds 2.0V

(typically), which is when the last value programmed is

recalled from EEPROM. On power-down, the I/OX state

is maintained until VCC drops below 1.9V (typically).

The internal pullups for each I/OX pin are controlled by

the pullup-enable register (F0h). Similarly, the individual

I/OX control registers (F4h to F7h) adjust the pulldown

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