DS4510 Datasheet, PDF (10/12 Pages) Maxim Integrated Products – CPU Supervisor with Nonvolatile Memory and Programmable I/O

CPU Supervisor with Nonvolatile Memory and
Programmable I/O
SDA
t_BUF
t_LOW
t_R
t_F
t_HD:STA
t_SP
SCL
t_HD:STA
STOP START
t_HD:DAT
t_HIGH
t_SU:DAT
t_SU:STA
REPEATED
START
t_SU:STO
NOTE: TIMING IS REFERENCE TO V_IL(MAX) AND V_IH(MIN)
Figure 5. I²C Timing Diagram
address pin allows for the DS4510 to respond to one of
two slave addresses (1010000X, or 1010001X). If the
R/W bit is zero, the master writes data to the slave. If
the R/W is one, the master reads data from the slave.
Memory Address: During an I²C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte (R/W = 0).
7-BIT SLAVE ADDRESS
1 0 1 0 0 0 A0 R/W
MOST
SIGNIFICANT BIT
A0 PIN
VALUE
DETERMINES
READ OR WRITE
Figure 6. DS4510’s Slave Address and the R/W Bit
I²C Communications
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address
(R/W= 0), write the memory address, write the byte of
data and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing a Multiple Bytes to a Slave: To write multiple
bytes to a slave the master generates a start condition,
writes the slave address (R/W = 0), writes the memory
address, writes up to 8 data bytes, and generates a
stop condition.
The DS4510 can write 1 to 8 bytes (one page or row)
with a single write transaction. This is internally con-
trolled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory table, see Figure 3). Attempts
to write to additional pages of memory without sending
a stop condition between pages results in the address
counter wrapping around to the beginning of the pre-
sent row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result would be address-
es 06h and 07h would contain 11h and 22h, respective-
ly, and the third data byte, 33h, would be written to
address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a stop condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. The master may then generate a new start con-
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