DS1340_11 Datasheet, PDF (8/16 Pages) Maxim Integrated Products – I2C RTC with Trickle Charger

I²C RTC with Trickle Charger
X1
X2
"C" VERSION ONLY
V_CC
V_BACKUP
SCL
SDA
C_L
C_L
POWER
CONTROL
SERIAL
INTERFACE
AND ADDRESS
REGISTER
32,768Hz
512Hz
DIVIDER AND
CALIBRATION
CIRCUIT
1Hz
CONTROL
LOGIC
MUX/
BUFFER
CLOCK AND
CALENDAR
REGISTERS
DS1340
USER BUFFER
(7 BYTES)
FT/OUT
N
Figure 5. Functional Diagram
Address Map
Table 3 shows the DS1340 address map. The RTC reg-
isters are located in address locations 00h to 06h, and
the control register is located at 07h. The trickle-charge
and flag registers are located in address locations 08h
to 09h. During a multibyte access of the timekeeping
registers, when the address pointer reaches 07h—the
end of the clock and control register space—it wraps
around to location 00h. Writing the address pointer to
the corresponding location accesses address locations
08h and 09h. After accessing location 09h, the address
pointer wraps around to location 00h. On a I²C START,
STOP, or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Table 3 shows the
RTC registers. The time and calendar data are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
Table 3. Address Map
ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
BIT 7
EOSC
X
CEB
X
X
X
OUT
TCS3
OSF
BIT 6 BIT 5 BIT 4
10 Seconds
10 Minutes
CB
10 Hours
X
X
X
X
10 Date
X
X
10 Month
10 Year
FT
S
CAL4
TCS2 TCS1 TCS0
0
0
0
BIT 3
X
CAL3
DS1
0
BIT 2
BIT 1
Seconds
Minutes
Hours
Day
Date
Month
Year
CAL2
CAL1
DS0
ROUT1
0
0
BIT 0
CAL0
ROUT0
0
FUNCTION
Seconds
Minutes
Century/Hours
Day
Date
Month
Year
Control
Trickle Charger
Flag
X = Read/Write bit
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
RANGE
00–59
00–59
0–1; 00–23
01–07
01–31
01–12
00–99
—
—
—
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