DS1340_11 Datasheet, PDF (11/16 Pages) Maxim Integrated Products – I2C RTC with Trickle Charger

I²C RTC with Trickle Charger
have a one-second interval where the calibration is per-
formed. Negative calibration blanks 128 cycles of the
32,768Hz oscillator, slowing the clock down. Positive
calibration inserts 256 cycles of the 32,768Hz oscillator,
speeding the clock up. If a binary 1 is loaded into the
calibration bits, only the first two minutes in the 64-
minute cycle are modified. If a binary 6 is loaded, the
first 12 minutes are affected, and so on. Therefore,
each calibration step either adds 512 or subtracts 256
oscillator cycles for every 125,829,120 actual 32,678Hz
oscillator cycles (64 minutes). This equates to
+4.068ppm or -2.034ppm of adjustment per calibration
step. If the oscillator runs at exactly 32,768Hz, each of
the 31 increments of the calibration bits would repre-
sent +10.7 or -5.35 seconds per month, corresponding
to +5.5 or -2.75 minutes per month.
For example, if using the FT function, a reading of
512.01024Hz would indicate a +20ppm oscillator fre-
quency error, requiring a -10(00 1010) value to be
loaded in the S bit and the five calibration bits.
Note: Setting the calibration bits does not affect the fre-
quency test output frequency. Also note that writing to
the control register resets the divider chain.
I²C Serial Data Bus
The DS1340 supports a bidirectional I²C bus and data
transmission protocol. A device that sends data onto
the bus is defined as a transmitter and a device receiv-
ing data as a receiver. The device that controls the
message is called a master. The devices that are con-
trolled by the master are slaves. A master device that
generates the serial clock (SCL), controls the bus
access, and generates the START and STOP condi-
tions must control the bus. The DS1340 operates as a
slave on the I²C bus. Connections to the bus are made
through the open-drain I/O lines SDA and SCL. Within
the bus specifications a standard mode (100kHz max
clock rate) and a fast mode (400kHz max clock rate)
are defined. The DS1340 works in both modes.
The following bus protocol has been defined (Figure 7):
• Data transfer can be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high are inter-
preted as control signals.
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
START data transfer: A change in the data line’s
state from high to low, while the clock line is high,
defines a START condition.
STOP data transfer: A change in the data line’s
state from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The data line’s state represents valid
data when, after a START condition, the data line is
stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between the
START and STOP conditions is not limited, and is
MSB FIRST
SDA
MSB
LSB
MSB
LSB
SLAVE
ADDRESS
R/W ACK
DATA
ACK
DATA
ACK/
NACK
SCL
1–7
8
9
1–7
8
9
1–7
8
9
IDLE START
CONDITION
Figure 7. I²C Data Transfer Overview
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP CONDITION
REPEATED START
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