DS1340_11 Datasheet, PDF (10/16 Pages) Maxim Integrated Products – I2C RTC with Trickle Charger

I²C RTC with Trickle Charger
Table 4. Trickle-Charge Register
TCS3
TCS2
TCS1
TCS0
DS1
X
X
X
X
0
X
X
X
X
1
X
X
X
X
X
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
0
0
DS0
ROUT1 ROUT0
FUNCTION
0
X
X
Disabled
1
X
X
Disabled
X
0
0
Disabled
1
0
1
No diode, 250Ω resistor
0
0
1
One diode, 250Ω resistor
1
1
0
No diode, 2kΩ resistor
0
1
0
One diode, 2kΩ resistor
1
1
1
No diode, 4kΩ resistor
0
1
1
One diode, 4kΩ resistor
0
0
0
Power-on reset value
pattern on 1010 enables the trickle charger. All other
patterns disable the trickle charger. The trickle charger
is disabled when power is first applied. The diode-
select (DS) bits (bits 2, 3) select whether or not a diode
is connected between V_CC and V_BACKUP. If DS is 01,
no diode is selected; if DS is 10, a diode is selected.
The ROUT bits (bits 0, 1) select the value of the resistor
connected between V_CC and V_BACKUP. Table 3 shows
the resistor selected by the resistor select (ROUT) bits
and the diode selected by the diode select (DS) bits.
Warning: The ROUT value of 250Ω must not be select-
ed whenever V_CC is greater than 3.63V.
The user determines diode and resistor selection
according to the maximum current desired for battery
or super cap charging (Table 4). The maximum charg-
ing current can be calculated as illustrated in the fol-
lowing example.
Assume that a 3.3V system power supply is applied to
V_CC and a super cap is connected to V_BACKUP. Also
assume that the trickle charger has been enabled with
a diode and resistor R2 between V_CC and V_BACKUP.
The maximum current I_MAX would therefore be calculat-
ed as follows:
I_MAX = (3.3V - diode drop) / R2 ≈ (3.3V - 0.7V) /
2kΩ ≈ 1.3mA
As the super cap charges, the voltage drop between
V_CC and V_BACKUP decreases and therefore the charge
current decreases.
Flag Register (09h)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator has stopped or was
stopped for some time period and may be used to
judge the validity of the clock and calendar data. This
bit is edge triggered and is set to logic 1 when the
internal circuitry senses that the oscillator has transi-
tioned from a normal run state to a STOP condition. The
following are examples of conditions that can cause the
OSF bit to be set:
1) The first time power is applied.
2) The voltages present on V_CC and V_BACKUP
are insufficient to support oscillation.
3) The EOSC bit is set to 1, disabling the
oscillator.
4) External influences on the crystal (e.g., noise,
leakage).
The OSF bit remains at logic 1 until written to logic 0. It
can only be written to logic 0. Attempting to write OSF
to logic 1 leaves the value unchanged.
Bits 6 to 0: All other bits in the flag register read as 0
and cannot be written.
Clock Calibration
The DS1340 provides a digital clock calibration feature
to allow compensation for crystal and temperature vari-
ations. The calibration circuit adds or subtracts counts
from the oscillator divider chain at the divide-by-256
stage. The number of pulses blanked (subtracted for
negative calibration) or inserted (added for positive cal-
ibration) depends upon the value loaded into the five
calibration bits (CAL4–CAL0) located in the control reg-
ister. Adding counts speeds the clock up and subtract-
ing counts slows the clock down.
The calibration bits can be set to any value between 0
and 31 in binary form. Bit 5 of the control register, S, is
the sign bit. A value of 1 for the S bit indicates positive
calibration, while a value of 0 represents negative cali-
bration. Calibration occurs within a 64-minute cycle.
The first 62 minutes in the cycle can, once per minute,
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