DS1340_06 Datasheet, PDF (8/14 Pages) Maxim Integrated Products – I2C RTC with Trickle Charger

I²C RTC with Trickle Charger
Address Map
Table 3 shows the DS1340 address map. The RTC reg-
isters are located in address locations 00h to 06h, and
the control register is located at 07h. The trickle-charge
and flag registers are located in address locations 08h
to 09h. During a multibyte access of the timekeeping
registers, when the address pointer reaches 07h—the
end of the clock and control register space—it wraps
around to location 00h. Writing the address pointer to
the corresponding location accesses address locations
08h and 09h. After accessing location 09h, the address
pointer wraps around to location 00h. On a I²C START,
STOP, or address pointer incrementing to location 00h,
the current time is transferred to a second set of regis-
ters. The time information is read from these secondary
registers, while the clock may continue to run. This
eliminates the need to reread the registers in case the
main registers update during a read.
Clock and Calendar
The time and calendar information is obtained by read-
ing the appropriate register bytes. Table 3 shows the
RTC registers. The time and calendar data are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The day-of-week
register increments at midnight. Values that correspond
to the day of week are user-defined but must be
sequential (i.e., if 1 equals Sunday, then 2 equals
Monday, and so on). Illogical time and date entries
result in undefined operation. Bit 7 of register 0 is the
enable oscillator (EOSC) bit. When this bit is set to 1, the
oscillator is disabled. When cleared to 0, the oscillator is
enabled. The initial power-up value of EOSC is 0.
Location 02h is the century/hours register. Bit 7 and bit
6 of the century/hours register are the century-enable
bit (CEB) and the century bit (CB). Setting CEB to logic
1 causes the CB bit to toggle, either from a logic 0 to a
logic 1, or from a logic 1 to a logic 0, when the years
register rolls over from 99 to 00. If CEB is set to logic 0,
CB does not toggle.
When reading or writing the time and date registers,
secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the
time and date registers, the user buffers are synchro-
nized to the internal registers on any START or STOP
and when the register pointer rolls over to zero. The
time information is read from these secondary registers
while the clock continues to run. This eliminates the
need to reread the registers in case the internal regis-
ters update during a read.
The divider chain is reset whenever the seconds regis-
ter is written. Write transfers occur on the acknowledge
from the DS1340. Once the divider chain is reset, to
avoid rollover issues, the remaining time and date reg-
isters must be written within one second.
Special-Purpose Registers
The DS1340 has three additional registers (control,
trickle charger, and flag) that control the RTC, trickle
charger, and oscillator flag output.
Table 3. Address Map
ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
BIT 7
EOSC
X
CEB
X
X
X
OUT
TCS3
OSF
BIT 6 BIT 5
BIT 4
10 Seconds
10 Minutes
CB
10 Hours
X
X
X
X
10 Date
X
X
10 Month
10 Year
FT
S
CAL4
TCS2 TCS1
TCS0
0
0
0
BIT 3
X
CAL3
DS1
0
BIT 2
BIT 1
Seconds
Minutes
Hours
Day
Date
Month
Year
CAL2
CAL1
DS0
ROUT1
0
0
BIT 0
CAL0
ROUT0
0
FUNCTION
Seconds
Minutes
Century/Hours
Day
Date
Month
Year
Control
Trickle Charger
Flag
X = Read/Write bit
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
RANGE
00–59
00–59
0–1; 00–23
01–07
01–31
01–12
00–99
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