DS1340_06 Datasheet, PDF (10/14 Pages) Maxim Integrated Products – I2C RTC with Trickle Charger

I²C RTC with Trickle Charger
Table 4. Trickle-Charge Register
TCS3
TCS2
TCS1
TCS0
DS1
X
X
X
X
0
X
X
X
X
1
X
X
X
X
X
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
1
0
1
0
0
1
0
1
0
1
0
0
0
0
0
DS0
ROUT1 ROUT0
FUNCTION
0
X
X
Disabled
1
X
X
Disabled
X
0
0
Disabled
1
0
1
No diode, 250Ω resistor
0
0
1
One diode, 250Ω resistor
1
1
0
No diode, 2kΩ resistor
0
1
0
One diode, 2kΩ resistor
1
1
1
No diode, 4kΩ resistor
0
1
1
One diode, 4kΩ resistor
0
0
0
Power-on reset value
Flag Register (09h)
Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit
indicates that the oscillator has stopped or was
stopped for some time period and may be used to
judge the validity of the clock and calendar data. This
bit is edge triggered and is set to logic 1 when the
internal circuitry senses that the oscillator has transi-
tioned from a normal run state to a STOP condition. The
following are examples of conditions that can cause the
OSF bit to be set:
1) The first time power is applied.
2) The voltages present on V_CC and V_BACKUP
are insufficient to support oscillation.
3) The EOSC bit is set to 1, disabling the
oscillator.
4) External influences on the crystal (e.g., noise,
leakage).
The OSF bit remains at logic 1 until written to logic 0. It
can only be written to logic 0. Attempting to write OSF
to logic 1 leaves the value unchanged.
Bits 6 to 0: All other bits in the flag register read as 0
and cannot be written.
Clock Calibration
The DS1340 provides a digital clock calibration feature
to allow compensation for crystal and temperature vari-
ations. The calibration circuit adds or subtracts counts
from the oscillator divider chain at the divide-by-256
stage. The number of pulses blanked (subtracted for
negative calibration) or inserted (added for positive cal-
ibration) depends upon the value loaded into the five
calibration bits (CAL4–CAL0) located in the control reg-
ister. Adding counts speeds the clock up and subtract-
ing counts slows the clock down.
The calibration bits can be set to any value between 0
and 31 in binary form. Bit 5 of the control register, S, is
the sign bit. A value of 1 for the S bit indicates positive
calibration, while a value of 0 represents negative cali-
bration. Calibration occurs within a 64-minute cycle.
The first 62 minutes in the cycle can, once per minute,
have a one-second interval where the calibration is per-
formed. Negative calibration blanks 128 cycles of the
32,768Hz oscillator, slowing the clock down. Positive
calibration inserts 256 cycles of the 32,768Hz oscillator,
speeding the clock up. If a binary 1 is loaded into the
calibration bits, only the first two minutes in the 64-
minute cycle are modified. If a binary 6 is loaded, the
first 12 minutes are affected, and so on. Therefore,
each calibration step either adds 512 or subtracts 256
oscillator cycles for every 125,829,120 actual 32,678Hz
oscillator cycles (64 minutes). This equates to
+4.068ppm or -2.034ppm of adjustment per calibration
step. If the oscillator runs at exactly 32,768Hz, each of
the 31 increments of the calibration bits would repre-
sent +10.7 or -5.35 seconds per month, corresponding
to +5.5 or -2.75 minutes per month.
For example, if using the FT function, a reading of
512.01024Hz would indicate a +20ppm oscillator fre-
quency error, requiring a -10(00 1010) value to be
loaded in the S bit and the five calibration bits.
Note: Setting the calibration bits does not affect the fre-
quency test output frequency. Also note that writing to
the control register resets the divider chain.
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