MAX15026_12 Datasheet, PDF (7/23 Pages) Maxim Integrated Products – Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller

Low-Cost, Small, 4.5V to 28V Wide Operating
Range, DC-DC Synchronous Buck Controller
Pin Description
PIN
NAME
FUNCTION
1
IN
Regulator Input. Bypass IN to GND with a 1µF minimum ceramic capacitor. Connect IN to V_CC when
operating in the 5V ±10% range.
5.25V Linear Regulator Output. Bypass V_CC to GND with a minimum of 4.7µF low-ESR ceramic
2
V_CC
capacitor to ensure stability up to the regulated rated current when V_CC supplies the drive current at
DRV. Bypass V_CC to GND when V_CC supplies the device core quiescent current with a 2.2µF
minimum ceramic capacitor.
3
PGOOD Open-Drain Power-Good Output. Connect PGOOD with an external resistor to any supply voltage.
4
EN
Active-High Enable Input. Pull EN to GND to disable the output. Connect EN to V_CC for always-on
operation. EN can be used for power sequencing and as a UVLO adjustment input.
5
LIM
Current-Limit Adjustment. Connect a resistor from LIM to GND to adjust current-limit threshold from
30mV (R_LIM = 6kΩ) to 300mV (R_LIM = 60kΩ). See the Setting the Valley Current Limit section.
6
COMP
Compensation Input. Connect compensation network from COMP to FB or from COMP to GND. See
the Compensation section.
7
FB
Feedback Input. Connect FB to a resistive divider between output and GND to adjust the output
voltage between 0.6V and (0.85 x Input Voltage). See the Setting the Output Voltage section.
8
RT
Oscillator Timing Resistor Input. Connect a resistor from RT to GND to set the oscillator frequency
from 200kHz to 2MHz. See the Setting the Switching Frequency section.
9
GND
Ground
10
DRV
Drive Supply Voltage. DRV is internally connected to the anode terminal of the internal boost diode.
Bypass DRV to GND with a 2.2µF minimum ceramic capacitor (see the Typical Application Circuits).
11
DL
Low-Side Gate-Driver Output. DL swings from DRV to GND. DL is low during UVLO.
12
BST
Boost Flying Capacitor. Connect a ceramic capacitor with a minimum value of 100nF between BST
and LX.
External Inductor Connection. Connect LX to the switching side of the inductor. LX serves as the
13
LX
lower supply rail for the high-side gate driver and as a sensing input of the drain to source voltage
drop of the synchronous MOSFET.
14
DH
High-Side Gate-Driver Output. DH swings from LX to BST. DH is low during UVLO.
—
EP
Exposed Pad. Internally connected to GND. Connect EP to a large copper plane at GND potential to
improve thermal dissipation. Do not use EP as the only GND ground connection.
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