MAX15026_12 Datasheet, PDF(17/23 Page) Maxim Integrated Products – Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller

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MAX15026_12 Datasheet, PDF (17/23 Pages) Maxim Integrated Products – Low-Cost, Small, 4.5V to 28V Wide Operating Range, DC-DC Synchronous Buck Controller

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Low-Cost, Small, 4.5V to 28V Wide Operating

Range, DC-DC Synchronous Buck Controller

The gain of the error amplifier (GAINEA) in midband fre-

quencies is:

GAINEA = 2Ï x fO x C1 x RF

The total loop gain as the product of the modulator gain

and the error amplifier gain at fO is 1.

GAINMOD Ã GAINEA = 1

So:

VIN

VRAMP

(2Ï

fO)2

COUT

LOUT

Solving for CI:

( ) CI =

VRAMP Ã

2Ï Ã fO Ã LOUT

VIN Ã RF

Ã COUT

3) Use the second pole (fP2) to cancel fZO when fPO <

fO < fZO < fSW/2. The frequency response of the

loop gain does not flatten out soon after the 0dB

crossover, and maintains a -20dB/decade slope up

to 1/2 of the switching frequency. This is likely to

occur if the output capacitor is a low-ESR tantalum.

Set fP2 = fZO.

When using a ceramic capacitor, the capacitor ESR

zero fZO is likely to be located even above 1/2 the

switching frequency, fPO < fO < fSW/2 < fZO. In this

case, place the frequency of the second pole (fP2) high

enough to not significantly erode the phase margin at

the crossover frequency. For example, set fP2 at 5 x fO

so that the contribution to phase loss at the crossover

frequency fO is only about 11Â°:

fP2 = 5 x fPO

Once fP2 is known, calculate RI:

2Ï

fP2

4) Place the second zero (fZ2) at 0.2 x fO or at fPO,

whichever is lower, and calculate R1 using the fol-

lowing equation:

2Ï

fZ2

5) Place the third pole (fP3) at 1/2 the switching fre-

quency and calculate CCF:

CCF

(2Ï

0.5 Ã

fSW Ã RF

CF ) â 1

6) Calculate R2 as:

VFB

VOUT â VFB

Ã R1

MOSFET Selection

The MAX15026 step-down controller drives two external

logic-level n-channel MOSFETs. The key selection

parameters to choose these MOSFETs include:

â¢ On-Resistance (RDS(ON))

â¢ Maximum Drain-to-Source Voltage (VDS(MAX))

â¢ Minimum Threshold Voltage (VTH(MIN))

â¢ Total Gate Charge (QG)

â¢ Reverse Transfer Capacitance (CRSS)

â¢ Power Dissipation

The two n-channel MOSFETs must be a logic-level type

with guaranteed on-resistance specifications at VGS =

4.5V. For maximum efficiency, choose a high-side

MOSFET that has conduction losses equal to the

switching losses at the typical input voltage. Ensure

that the conduction losses at minimum input voltage do

not exceed the MOSFET package thermal limits, or vio-

late the overall thermal budget. Also, ensure that the

conduction losses plus switching losses at the maxi-

mum input voltage do not exceed package ratings or

violate the overall thermal budget. Ensure that the DL

gate driver can drive the low-side MOSFET. In particu-

lar, check that the dv/dt caused by the high-side

MOSFET turning on does not pull up the low-side

MOSFET gate through the drain-to-gate capacitance

of the low-side MOSFET, which is the most frequent

cause of cross-conduction problems.

Check power dissipation when using the internal linear

regulator to power the gate drivers. Select MOSFETs

with low gate charge so that VCC can power both dri-

vers without overheating the device.

PDRIVE = VCC x QG_TOTAL x fSW

where QG_TOTAL is the sum of the gate charges of the

two external MOSFETs.

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