DS8102 Datasheet, PDF (7/9 Pages) Maxim Integrated Products – Dual Delta-Sigma Modulator and Encoder

Dual Delta-Sigma Modulator and Encoder
Internal/External Voltage Reference
Selection
The configuration pin APDREF selects whether the
DS8102 uses its internal voltage reference or an exter-
nal voltage reference provided at V_REF when perform-
ing conversions. If the internal voltage reference is
selected, the internal reference is buffered and driven
out at V_REF, and can be used by external devices if
desired.
Table 2 summarizes the modes of operation for the
DS8102 based on the APDREF input. The level at
APDREF should be set when the DS8102 is in shut-
down mode.
Internal/External Clock Selection
The configuration input pin CLKSEL selects whether the
DS8102 uses the internal 8MHz oscillator or an external
clock (provided at CLKIO) when performing conver-
sions. If the internal 8MHz oscillator is selected, the
internal clock is driven out at CLKIO and can be used
by external devices if desired.
Table 3 summarizes the modes of operation for the
DS8102 based on the CLKSEL input. The level at
CLKSEL should be set when the DS8102 is in shutdown
mode.
Manchester Encoder
Once the DS8102 enters active mode, it begins gener-
ating a Manchester-encoded bit stream on the MNOUT
pin. This bit stream is output at a rate equal to the
selected clock frequency divided by 4, so, for example,
if the internal 8MHz oscillator is selected as the DS8102
clock source, a new bit is output on MNOUT approxi-
mately every 500ns.
Bit values are encoded as either low-to-high transitions
(for bit values of 1) or high-to-low transitions (for bit val-
ues of 0). The transition from low-to-high or high-to-low
occurs halfway through the bit time slot.
As shown in Figure 1, the Manchester-encoded bit-
stream output on MNOUT contains three interleaved bit
streams. These bit streams, in the order that they are
output, are as follows:
1) SYNC—Synchronization bit stream containing alter-
nating 0s and 1s.
2) CHAN0—Pulse-density-modulated output from ana-
log channel 0.
3) CHAN1—Pulse-density-modulated output from ana-
log channel 1.
Both modulator outputs are always included in the bit
stream, even if only one of them is being used by the
application. This means that the maximum bit-rate out-
put for either modulator channel over MNOUT is
f_CLK/12 as shown in Figure 1.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line is either a best straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified.
Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal point.
Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) is the ratio of
changes in the power supply (V) to changes in the con-
verter output (V). It is typically measured in decibels.
Table 2. Voltage Reference Selection and Operating Modes
RST PIN
0
1
1
APDREF PIN
X
0
1
DS8102 MODE
Shutdown.
Operation using internal voltage reference (V_REF output buffer enabled).
Operation using external voltage reference (V_REF output buffer disabled).
Table 3. Clock Source Selection
CLKSEL PIN
0
1
DS8102 CLOCK SOURCE
Internal 8MHz oscillator
External clock (provided at CLKIO)
CLKIO PIN MODE
Output: Drives out 8MHz clock.
Input: Accepts external clock.
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