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DS8102 Datasheet, PDF (3/9 Pages) Maxim Integrated Products – Dual Delta-Sigma Modulator and Encoder
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Dual Delta-Sigma Modulator and Encoder
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V, TA = -40°C to +85°C, fCLK = 8MHz, VREF = internal, OSR = 128, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
(Note 2)
MAX
UNITS
ANALOG-TO-DIGITAL CONVERTER DYNAMIC SPECIFICATIONS
DC Power-Supply Rejection Ratio
PSRR
VDD = 3.0V to 3.6V, AN0+ = AN0- = AGND,
100mV ripple on VDD
95
dB
VDD = 3.6V, gain = 1, AN0 = 500mVP-P,
70
85
sinewave at 62.5Hz
Signal-to-Noise Ratio
SINAD
dB
VDD = 3.6V, gain = 32, AN0 = 20mVP-P,
sinewave at 62.5Hz
70
85
Total Harmonic Distortion
(to 21st Harmonic)
THD
ANALOG-TO-DIGITAL CONVERTER INPUTS
VDD = 3.6V, gain = 32, AN0 = 20mVP-P,
sinewave at 62.5Hz
-95
-70
dB
Input Voltage Range
AN0+, AN0-, AN1+, and AN1- to AGND
-1
+1
V
Gain = 1
1
Input Sampling Capacitance
(Note 1)
Gain = 4
CIN
Gain = 16
4
pF
16
Gain = 32
32
Input Sampling Rate
fS
Clock at 8MHz (Note 7)
Gain = 1
0.667
750
MHz
Input Impedance to AGND for
8MHz (Note 8)
Gain = 4
Gain = 16
187
k
47
Gain = 32
23.4
Gain = 1
1500
Differential Input Impedance for
8MHz (Note 9)
Gain = 4
Gain = 16
375
k
94
Gain = 32
46.9
Input Bandwidth (-3dB)
7
kHz
External Reference Input Voltage
External Reference Input
Sampling Capacitance
Reference Input Sampling Rate
INTERNAL REFERENCE
VREF
fS
1.2 1.25 1.3
V
2
pF
0.67
1
MHz
Reference Output Voltage
1.24
V
Reference Output Temperature
Coefficient
±30
ppm/°C
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: Typical values are not guaranteed. These values are measured at room temperature, VDD = 3.3V.
Note 3: These numbers are guaranteed by design and are not tested.
Note 4: Calculated as tWU1 = 1/fICLK x 8192.
Note 5: Calculated as tWU2 = 1/fICLK x 57,344.
Note 6: Parameter specifications are based upon the presence of an external cubic sinc filter (as implemented in the MAXQ3108)
for generating full ADC output codewords.
Note 7: fS = fCLK/12. fCLK is the system clock frequency.
Note 8: This is a function of input sampling capacitance (CIN) and sampling frequency, and can be approximated as 6/(fCLK x CIN).
Note 9: ZIN (differential) = 2 x ZIN (single-ended).
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