DS8102 Datasheet, PDF (2/9 Pages) Maxim Integrated Products – Dual Delta-Sigma Modulator and Encoder

Dual Delta-Sigma Modulator and Encoder
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V_DD Relative to DGND.............-0.3V to +4.0V
Voltage Range on V_DD Relative to AGND .............-0.3V to +4.0V
Voltage Range on AGND Relative to DGND .........-0.3V to +0.3V
Voltage Range on Any Pin Relative to DGND
Except AN0+, AN0-, and AN1+, AN1- ...............-0.3V to +4.0V
Voltage Range on AN0+, AN0-, AN1+, and AN1-
Relative to AGND ...............................................-4.0V to +4.0V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V_DD = 2.7V to 3.6V, T_A = -40°C to +85°C, f_CLK = 8MHz, V_REF = internal, OSR = 128, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
Power-Fail Reset Voltage
Active V_DD Current
Shutdown (Power-Down) V_DD
Current
V_DD
V_RST
I_DD
I_STOP
Monitors V_DD
Normal operation
RST = 0 or V_DD < V_RST
Input Low Voltage
Input High Voltage
Output Low Voltage
(CLKIO, MNOUT)
V_IL
V_IH
V_OL
I_OL = 4mA
Output High Voltage
(CLKIO, MNOUT)
V_OH
I_OH = -4mA
Input/Output Pin Capacitance
Input Leakage Current (All Inputs)
CLOCK SOURCE
C_IO
(Note 3)
I_L
External Clock Input Frequency
External Clock Input Period
External Clock Input Duty Cycle
f_XCLK
t_XCLK-CLCL
t_XCLK-DUTY
CLKSEL = 1
CLKSEL = 1
CLKSEL = 1
Internal Oscillator Output
Frequency
f_ICLK CLKSEL = 0
Internal Oscillator Output Duty
Cycle
t_ICLK-DUTY CLKSEL = 0
ANALOG-TO-DIGITAL CONVERTER
AFE Warmup Delay
Reference Buffer Warmup Delay
t_WU1
t_WU2
f_ICLK = 8MHz (Notes 1, 4)
f_ICLK = 8MHz (Notes 1, 5)
OSR = 32
Decimator Output (Note 6)
OSR = 64
OSR = 128
OSR = 256
Integral Nonlinearity
INL
(Notes 1, 6)
Offset Error
Gain = 1 (Note 6)
MIN
V_RST
2.7
TYP
(Note 2)
3.3
2.8
3.5
MAX
3.6
2.99
5.0
UNITS
V
V
mA
2
nA
DGND
0.7 x V_DD
0.3 x V_DD V
V_DD
V
DGND
0.4
V
V_DD - 0.4
-100
V
15
pF
+100
nA
DC
8
MHz
125
ns
40
60
%
7.5
8.0
8.5
MHz
47.8 49.1 49.7
%
16
19
22
24
±0.01
1.02
7.17
1.4
ms
ms
Bits
%FSR
mV
2 _______________________________________________________________________________________