Z86L81 Datasheet, PDF (60/88 Pages) Maxim Integrated Products – 28-Pin Low-Voltage Infrared Microcontrollers

Z86L81/86/98
28-Pin Low-Voltage Infrared Microcontrollers
54
PCON (FH) 00H
D7 D6 D5 D4 D3 D2 D1 D0
* Default setting after reset
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 0
0: Open-Drain
1: Push-Pull
Reserved (Must be 1)
Figure 28. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the compar-
ator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configu-
ration.
Port0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop-
Mode Recovery (Figure 29). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of STOP recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input is required from the recovery source. Bit 5 controls the reset delay after
recovery. Bits D2, D3, and D4, or the SMR register, specify the source of the Stop-
Mode Recovery signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not.
The SMR is located in Bank F of the Expanded Register Group at address 0Bh.
19-4615; Rev 0; 4/09