MAX1361 Datasheet, PDF (6/24 Pages) Maxim Integrated Products – 4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response

4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
ELECTRICAL CHARACTERISTICS (continued)
(V_DD = 2.7V to 3.6V (MAX1361), V_DD = 4.5V to 5.5V (MAX1362), V_REF = 2.048V (MAX1361), V_REF = 4.096V (MAX1362), C_REF =
0.1µF, f_SCL = 1.7MHz, T_A = T_MIN to T_MAX, unless otherwise noted. Typical values are at T_A = +25°C.)
Note 1: Devices configured for unipolar single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain and offset have
been calibrated.
Note 3: Offset nulled.
Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
Note 5: The throughput rate of the I²C bus is limited to 94.4ksps. The MAX1361/MAX1362 can perform conversions up to 150ksps
in monitor mode when not reading back results on the I²C bus.
Note 6: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
Note 7: The absolute input voltage range for the analog inputs (AIN0–AIN3) is from GND to V_DD.
Note 8: When the internal reference is configured to be available at AIN3/REF (SEL[2:1] = 11), decouple AIN3/REF to GND with a
0.01µF capacitor.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µV_P-P.
Note 10: Maximum conversion throughput in internal clock mode when the data is not clocked out.
Note 11: For the MAX1361, PSRR is measured as
[ ] ^



V_FS (3.6V) − V_FS (2.7V)
×
2^N − 1^
V_REF


(3.6V − 2.7V)
and for the MAX1362, PSRR is measured as
[ ] ^



V_FS (5.5V) − V_FS (4.5V)
×
2^N − 1^
V_REF


(5.5V − 4.5V)
Note 12: C_B = total capacitance of one bus line in pF.
Note 13: f_SCLH must meet the minimum clock low time plus the rise/fall times.
Note 14: A master device must provide a data hold time for SDA (referred to V_IL of SCL) to bridge the undefined region of SCL’s
falling edge.
Typical Operating Characteristics
(V_DD = 3.3V (MAX1361), V_DD = 5V (MAX1362), f_SCL = 1.7MHz, external clock, f_SAMPLE = 94.4ksps, single-ended, unipolar,
T_A = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
0
200 400 600 800 1000
DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0
INTEGRAL NONLINEARITY
vs. DIGITAL CODE
200 400 600 800 1000
DIGITAL OUTPUT CODE
0
-20
-40
-60
-80
-100
-120
-140
-160
0
FFT PLOT
f_SAMPLE = 94.4ksps
f_IN = 10kHz
10
20
30
40
50
FREQUENCY (kHz)
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