MAX1361 Datasheet, PDF (19/24 Pages) Maxim Integrated Products – 4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response

4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
Table 9. Monitor-Mode Setup Data Format
Alarm reset, scan
speed, INT_EN ,
(8 bits)
AIN0 thresholds
(24 bits)
AIN1 thresholds
(skip if differential mode, or
CS1, CS0 < 1) (24 bits)
AIN2 thresholds (skip if AIN3 thresholds (skip if differential
CS1, CS0 < 2)
mode, or CS1, CS0 < 3)
(24 bits)
(24 bits)
Table 10. Alarm Reset, Scan Speed Register, and INT_EN Data Format
RESET
RESET
RESET
RESET
ALARM CH 0 ALARM CH 1 ALARM CH 2 ALARM CH 3
0/1
0/1
0/1
0/1
DELAY 2
0/1
DELAY 1
0/1
DELAY 0
0/1
INT_EN
0/1
Table 11. Delay Settings
DELAY 2 DELAY 1 DELAY 0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MONITOR-MODE
CONVERSION RATE
(ksps)
150.0*
75.0
37.5
18.8
9.4
4.7
2.3
1.2
*When using delay = [0,0,0] in internal reference mode and
AIN3/REF configured as a REF output, the MAX1361/MAX1362
may exhibit a code-dependant gain error due to insufficient
internal reference drive. Gain error caused by this phenomenon
is typically less than 1%FSR (0.1µF C_REF in series with a 2kΩ
resistor) and increases with a larger C_REF. Avoid this gain error
by using an external reference, V_DD, as a reference or use an
internal reference with AIN3/REF as an analog input (see Table
4). Alternatively, choose delay bits other than [0,0,0] to lower the
conversion rate.
A 1 written to the reset alarm CH_ clears the alarm, oth-
erwise no action occurs (Table 10). Deassert INT by
clearing all alarms or by initiating an SMBus alert dur-
ing an alarm condition (see the SMBus Alert section)
The Delay 2, Delay 1, Delay 0 bits set the speed of
monitoring by changing the delay between conver-
sions. Delay 2, 1, 0 = 000 sets the maximum possible
speed; 001 divides the maximum speed by ~2.
Increasing delay values further divides the previous
speed by two (Table 11).
INT_EN controls the open-drain INT output. Set INT_EN
to 1 to enable the hardware interrupt. Set INT_EN to 0
to disable the hardware interrupt output. The INT output
is high impedance when disabled or when there are no
alarms. The master can also poll the alarm status regis-
ter at any time to check the alarm status.
Repeat clocking channel threshold data up to the chan-
nel programmed by CS1 and CS0 (Table 12). For differ-
ential input mode, omit odd channels; the lower and
upper threshold data applies to channel pairs. There is
no need to clock in dummy data for odd (or even)
channels (Table 6).
Table 12. Lower and Upper Threshold Data Format
BYTE
B7
1
X
B6
B5
B4
B3
B2
X
LT9
LT8
LT7
LT6
(MSB)
2
LT3
LT2
LT1
LT0 (LSB)
X
X
3
UT7
UT6
UT5
UT4
UT3
UT2
X = Don’t care.
ACK = Acknowledge.
B1
B0
ACKNOWLEDGE
LT5
LT4
ACK
UT9
(MSB)
UT1
UT8
UT0 (LSB)
ACK
ACK
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