MAX1361 Datasheet, PDF (13/24 Pages) Maxim Integrated Products – 4-Channel, 10-Bit, System Monitors with Programmable Trip Window and SMBus Alert Response

4-Channel, 10-Bit, System Monitor with Programmable
Trip Window and SMBus Alert Response
SLAVE ADDRESS
S
0
1
1
0
1
0
0
R/W
ACK
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 6. MAX1361/MAX1362 Slave Address Byte
Table 1. I²C Slave Selection Table
A0 STATE
Low
High
Low
High
Low
High
SUFFIX
EUB
EUB
MEUB
MEUB
LEUB
LEUB
ADDRESS
0110100
0110101
0110110
0110111
0110010
0110011
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master reattempts com-
munication at a later time.
Slave Address
The MAX1361/MAX1362 have a 7-bit I²C slave
address. The slave address is selected using A0. The
MAX1361/MAX1362 (EUB, MEUB, and LEUB) have 3
base address options, allowing up to 6 devices concur-
rently per I²C bus (see Table 1).
The MAX1361/MAX1362 continuously wait for a START
condition followed by its slave address. When the device
recognizes its slave address, it is ready to accept or
send data depending on the R/W bit (Figure 6).
HS I²C Mode
At power-up, the MAX1361/MAX1362 bus timing is set
for fast mode (F/S mode, up to 400kHz I²C clock), which
limits the conversion rate to approximately 22ksps.
Switch to high-speed mode (HS mode, up to 1.7MHz
I²C clock) to achieve conversion rates up to 94.4ksps.
The MAX1361/MAX1362 convert up to 150ksps in moni-
tor mode, regardless of I²C mode. If conversion results
are unread, I²C bandwidth limitations do not apply in
monitor mode.
Select HS mode by addressing all devices on the bus
with the HS-mode master code 0000 1XXX (X = don’t
care). After successfully receiving the HS-mode master
code, the MAX1361/MAX1362 issue a NACK, allowing
SDA to be pulled high for one clock cycle (Figure 7).
After the NACK, the MAX1361/MAX1362 operate in HS
mode. Send a repeated START (Sr) followed by a slave
address to initiate HS-mode communication. If the mas-
ter generates a STOP condition the MAX1361/MAX1362
S
0
SDA
HS-MODE MASTER CODE
0
0
0
1
X
X
X
NACK
Sr
SCL
Figure 7. F/S-Mode to HS-Mode Transfer
F/S MODE
HS MODE
______________________________________________________________________________________ 13