MAX13202E Datasheet, PDF (6/9 Pages) Maxim Integrated Products – 2-/4-/6-/8-Channel, ±30kV ESD Protectors in μDFN

2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
R_C
50Ω to 100Ω
CHARGE-CURRENT-
LIMIT RESISTOR
R_D
330Ω
DISCHARGE
RESISTANCE
HIGH-
VOLTAGE
DC
SOURCE
Cs
150pF
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
Figure 6. IEC 61000-4-2 ESD Test Model
Human Body Model
Figure 4 shows the Human Body Model, and Figure 5
shows the current waveform it generates when dis-
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
est, which is then discharged into the device through a
1.5kΩ resistor.
IEC 61000-4-2
The IEC 61000-4-2 standard covers ESD testing and
performance of finished equipment. The MAX13202E/
MAX13204E/MAX13206E/MAX13208E help users
design equipment that meets Level 4 of IEC 61000-4-2.
The main difference between tests done using the
Human Body Model and IEC 61000-4-2 is higher peak
current in IEC 61000-4-2. Because series resistance is
lower in the IEC 61000-4-2 ESD test model (Figure 6),
the ESD-withstand voltage measured to this standard is
generally lower than that measured using the Human
Body Model. Figure 3 shows the current waveform for
the ±8kV IEC 61000-4-2 Level 4 ESD Contact
Discharge test.
The Air-Gap Discharge test involves approaching the
device with a charged probe. The Contact Discharge
method connects the probe to the device before the
probe is energized.
Layout Recommendations
Proper circuit-board layout is critical to suppress ESD-
induced line transients. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E clamp to ±120V; however, with
improper layout, the voltage spike at the device is much
higher. A lead inductance of 10nH with a 45A current
spike at a dv/dt of 1ns results in an ADDITIONAL 450V
spike on the protected line. It is essential that the layout
of the PC board follows these guidelines:
1) Minimize trace length between the connector or
input terminal, I/O_, and the protected signal line.
2) Use separate planes for power and ground to reduce
parasitic inductance and to reduce the impedance to
the power rails for shunted ESD current.
3) Ensure short ESD transient return paths to GND
and V_CC.
4) Minimize conductive power and ground loops.
5) Do not place critical signals near the edge of the
PC board.
6) Bypass V_CC to GND with a low-ESR ceramic capaci-
tor as close to V_CC and ground terminals as possible.
7) Bypass the supply of the protected device to GND
with a low-ESR ceramic capacitor as close to the
supply pin as possible.
PROCESS: BiCMOS
Chip Information
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