MAX13202E Datasheet, PDF (4/9 Pages) Maxim Integrated Products – 2-/4-/6-/8-Channel, ±30kV ESD Protectors in μDFN

2-/4-/6-/8-Channel, ±30kV ESD Protectors in µDFN
Detailed Description
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are diode arrays designed to protect sensitive electron-
ics against damage resulting from ESD conditions or
transient voltages. The low input capacitance makes
these devices ideal for high-speed data lines. The
MAX13202E/MAX13204E/MAX13206E/MAX13208E
protect two, four, six, and eight channels, respectively.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
are designed to work in conjunction with a device’s
intrinsic ESD protection. The MAX13202E/MAX13204E/
MAX13206E/MAX13208E limit the excursion of the ESD
event to below ±25V peak voltage when subjected to the
Human Body Model waveform. When subjected to the
IEC 61000-4-2 waveform, the peak voltage is limited to
±80V (Contact Discharge) and ±120V (Air-Gap
Discharge). The device that is being protected by the
MAX13202E/MAX13204E/ MAX13206E/MAX13208E
must be able to withstand these peak voltages plus any
additional voltage generated by the parasitic board.
Applications Information
Design Considerations
Maximum protection against ESD damage results from
proper board layout (see the Layout Recommendations
section and Figure 2). A good layout reduces the para-
sitic series inductance on the ground line, supply line,
and protected signal lines.
The MAX13202E/MAX13204E/MAX13206E/MAX13208E
ESD diodes clamp the voltage on the protected lines
during an ESD event and shunt the current to GND or
V_CC. In an ideal circuit, the clamping voltage, V_C, is
defined as the forward voltage drop, V_F, of the protection
diode plus any supply voltage present on the cathode.
For positive ESD pulses:
V_C = V_CC + V_F
For negative ESD pulses:
V_C = -V_F
In reality, the effect of the parasitic series inductance
on the lines must also be considered (Figure 1).
For positive ESD pulses:
V_C
=
V_CC
+
V_F(D1)
+
_{L1 x}
d(I_ESD
dt
)


+
_L2
x
d(I_ESD
dt
)


For negative ESD pulses:
V_C
=

− _ V_F(D2)
+
_{L1 x}
d(I_ESD)
dt


+
_L3
x
d(I_ESD )
dt




where I_ESD is the ESD current pulse.
POSITIVE SUPPLY RAIL
L2
D1
L1
I/O_
PROTECTED
LINE
D2
L3
GROUND RAIL
Figure 1. Parasitic Series Inductance
V_CC
L1
PROTECTED LINE
NEGATIVE ESD
CURRENT
PULSE
PATH TO
GROUND
GND
L2
D1
I/O_
D2
L3
V_C
PROTECTED
CIRCUIT
Figure 2. Layout Considerations
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